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target/ppc: Use tcg_constant_i64() in gen_brh()

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The mask of the Byte-Reverse Halfword opcode is a read-only
constant. We can avoid using a TCG temporary by moving the
mask to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211003141711.3673181-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-03 16:17:11 +02:00 committed by David Gibson
parent 6f4912a416
commit 491b3cca36
1 changed files with 3 additions and 5 deletions
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8
target/ppc/translate.c
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@ -7569,18 +7569,16 @@ static void gen_brw(DisasContext *ctx)
/* brh */
static void gen_brh(DisasContext *ctx)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
tcg_gen_and_i64(t2, t1, t0);
tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
tcg_gen_and_i64(t2, t1, mask);
tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
tcg_gen_shli_i64(t1, t1, 8);
tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}