ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture. Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu> [PMM: Minor tweaks and code cleanup, switch to ONE_REG] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Christoffer Dall
Peter Maydell
parent
f5206413af
commit
494b00c76a
26
hw/arm_pic.c
26
hw/arm_pic.c
@ -9,6 +9,7 @@
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#include "hw.h"
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#include "arm-misc.h"
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#include "sysemu/kvm.h"
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/* Input 0 is IRQ and input 1 is FIQ. */
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static void arm_pic_cpu_handler(void *opaque, int irq, int level)
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@ -34,7 +35,32 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
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}
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}
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static void kvm_arm_pic_cpu_handler(void *opaque, int irq, int level)
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{
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#ifdef CONFIG_KVM
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ARMCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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switch (irq) {
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case ARM_PIC_CPU_IRQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
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break;
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case ARM_PIC_CPU_FIQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
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break;
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default:
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hw_error("kvm_arm_pic_cpu_handler: Bad interrupt line %d\n", irq);
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}
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
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#endif
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}
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qemu_irq *arm_pic_init_cpu(ARMCPU *cpu)
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{
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if (kvm_enabled()) {
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return qemu_allocate_irqs(kvm_arm_pic_cpu_handler, cpu, 2);
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}
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return qemu_allocate_irqs(arm_pic_cpu_handler, cpu, 2);
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}
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@ -1,4 +1,5 @@
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obj-y += arm-semi.o
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obj-$(CONFIG_SOFTMMU) += machine.o
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obj-$(CONFIG_KVM) += kvm.o
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obj-y += translate.o op_helper.o helper.o cpu.o
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obj-y += neon_helper.o iwmmxt_helper.o
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@ -237,6 +237,7 @@ void arm_translate_init(void);
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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int cpu_arm_exec(CPUARMState *s);
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void do_interrupt(CPUARMState *);
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int bank_number(int mode);
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void switch_mode(CPUARMState *, int);
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uint32_t do_arm_semihosting(CPUARMState *env);
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@ -1617,7 +1617,7 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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#else
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number(int mode)
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int bank_number(int mode)
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{
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switch (mode) {
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case ARM_CPU_MODE_USR:
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334
target-arm/kvm.c
Normal file
334
target-arm/kvm.c
Normal file
@ -0,0 +1,334 @@
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/*
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* ARM implementation of KVM hooks
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*
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* Copyright Christoffer Dall 2009-2010
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <stdio.h>
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "cpu.h"
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#include "hw/arm-misc.h"
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO
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};
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int kvm_arch_init(KVMState *s)
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{
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/* For ARM interrupt delivery is always asynchronous,
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* whether we are using an in-kernel VGIC or not.
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*/
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kvm_async_interrupts_allowed = true;
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return 0;
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}
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unsigned long kvm_arch_vcpu_id(CPUState *cpu)
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{
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return cpu->cpu_index;
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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struct kvm_vcpu_init init;
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init.target = KVM_ARM_TARGET_CORTEX_A15;
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memset(init.features, 0, sizeof(init.features));
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return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
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}
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typedef struct Reg {
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uint64_t id;
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int offset;
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} Reg;
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#define COREREG(KERNELNAME, QEMUFIELD) \
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
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offsetof(CPUARMState, QEMUFIELD) \
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}
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#define CP15REG(CRN, CRM, OPC1, OPC2, QEMUFIELD) \
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | \
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(15 << KVM_REG_ARM_COPROC_SHIFT) | \
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((CRN) << KVM_REG_ARM_32_CRN_SHIFT) | \
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((CRM) << KVM_REG_ARM_CRM_SHIFT) | \
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((OPC1) << KVM_REG_ARM_OPC1_SHIFT) | \
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((OPC2) << KVM_REG_ARM_32_OPC2_SHIFT), \
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offsetof(CPUARMState, QEMUFIELD) \
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}
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static const Reg regs[] = {
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/* R0_usr .. R14_usr */
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COREREG(usr_regs.uregs[0], regs[0]),
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COREREG(usr_regs.uregs[1], regs[1]),
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COREREG(usr_regs.uregs[2], regs[2]),
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COREREG(usr_regs.uregs[3], regs[3]),
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COREREG(usr_regs.uregs[4], regs[4]),
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COREREG(usr_regs.uregs[5], regs[5]),
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COREREG(usr_regs.uregs[6], regs[6]),
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COREREG(usr_regs.uregs[7], regs[7]),
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COREREG(usr_regs.uregs[8], usr_regs[0]),
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COREREG(usr_regs.uregs[9], usr_regs[1]),
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COREREG(usr_regs.uregs[10], usr_regs[2]),
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COREREG(usr_regs.uregs[11], usr_regs[3]),
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COREREG(usr_regs.uregs[12], usr_regs[4]),
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COREREG(usr_regs.uregs[13], banked_r13[0]),
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COREREG(usr_regs.uregs[14], banked_r14[0]),
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/* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
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COREREG(svc_regs[0], banked_r13[1]),
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COREREG(svc_regs[1], banked_r14[1]),
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COREREG(svc_regs[2], banked_spsr[1]),
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COREREG(abt_regs[0], banked_r13[2]),
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COREREG(abt_regs[1], banked_r14[2]),
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COREREG(abt_regs[2], banked_spsr[2]),
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COREREG(und_regs[0], banked_r13[3]),
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COREREG(und_regs[1], banked_r14[3]),
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COREREG(und_regs[2], banked_spsr[3]),
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COREREG(irq_regs[0], banked_r13[4]),
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COREREG(irq_regs[1], banked_r14[4]),
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COREREG(irq_regs[2], banked_spsr[4]),
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/* R8_fiq .. R14_fiq and SPSR_fiq */
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COREREG(fiq_regs[0], fiq_regs[0]),
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COREREG(fiq_regs[1], fiq_regs[1]),
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COREREG(fiq_regs[2], fiq_regs[2]),
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COREREG(fiq_regs[3], fiq_regs[3]),
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COREREG(fiq_regs[4], fiq_regs[4]),
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COREREG(fiq_regs[5], banked_r13[5]),
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COREREG(fiq_regs[6], banked_r14[5]),
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COREREG(fiq_regs[7], banked_spsr[5]),
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/* R15 */
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COREREG(usr_regs.uregs[15], regs[15]),
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/* A non-comprehensive set of cp15 registers.
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* TODO: drive this from the cp_regs hashtable instead.
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*/
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CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */
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CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */
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CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */
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};
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int kvm_arch_put_registers(CPUState *cs, int level)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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struct kvm_one_reg r;
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int mode, bn;
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int ret, i;
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uint32_t cpsr;
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uint64_t ttbr;
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/* Make sure the banked regs are properly set */
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mode = env->uncached_cpsr & CPSR_M;
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bn = bank_number(mode);
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if (mode == ARM_CPU_MODE_FIQ) {
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memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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} else {
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memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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}
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env->banked_r13[bn] = env->regs[13];
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env->banked_r14[bn] = env->regs[14];
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env->banked_spsr[bn] = env->spsr;
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/* Now we can safely copy stuff down to the kernel */
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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r.id = regs[i].id;
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r.addr = (uintptr_t)(env) + regs[i].offset;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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}
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/* Special cases which aren't a single CPUARMState field */
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cpsr = cpsr_read(env);
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
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r.addr = (uintptr_t)(&cpsr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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/* TTBR0: cp15 crm=2 opc1=0 */
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ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
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(2 << KVM_REG_ARM_CRM_SHIFT) | (0 << KVM_REG_ARM_OPC1_SHIFT);
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r.addr = (uintptr_t)(&ttbr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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/* TTBR1: cp15 crm=2 opc1=1 */
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ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
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(2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT);
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r.addr = (uintptr_t)(&ttbr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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return ret;
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}
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int kvm_arch_get_registers(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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struct kvm_one_reg r;
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int mode, bn;
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int ret, i;
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uint32_t cpsr;
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uint64_t ttbr;
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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r.id = regs[i].id;
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r.addr = (uintptr_t)(env) + regs[i].offset;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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}
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/* Special cases which aren't a single CPUARMState field */
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
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r.addr = (uintptr_t)(&cpsr);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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cpsr_write(env, cpsr, 0xffffffff);
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/* TTBR0: cp15 crm=2 opc1=0 */
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
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(2 << KVM_REG_ARM_CRM_SHIFT) | (0 << KVM_REG_ARM_OPC1_SHIFT);
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r.addr = (uintptr_t)(&ttbr);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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env->cp15.c2_base0_hi = ttbr >> 32;
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env->cp15.c2_base0 = ttbr;
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/* TTBR1: cp15 crm=2 opc1=1 */
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
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(2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT);
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r.addr = (uintptr_t)(&ttbr);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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env->cp15.c2_base1_hi = ttbr >> 32;
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env->cp15.c2_base1 = ttbr;
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/* Make sure the current mode regs are properly set */
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mode = env->uncached_cpsr & CPSR_M;
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bn = bank_number(mode);
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if (mode == ARM_CPU_MODE_FIQ) {
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memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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} else {
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memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
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}
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env->regs[13] = env->banked_r13[bn];
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env->regs[14] = env->banked_r14[bn];
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env->spsr = env->banked_spsr[bn];
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/* The main GET_ONE_REG loop above set c2_control, but we need to
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* update some extra cached precomputed values too.
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* When this is driven from the cp_regs hashtable then this ugliness
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* can disappear because we'll use the access function which sets
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* these values automatically.
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*/
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env->cp15.c2_mask = ~(0xffffffffu >> env->cp15.c2_control);
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env->cp15.c2_base_mask = ~(0x3fffu >> env->cp15.c2_control);
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return 0;
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}
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void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
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{
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}
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void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
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{
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}
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int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
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{
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return 0;
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}
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void kvm_arch_reset_vcpu(CPUState *cs)
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{
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}
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bool kvm_arch_stop_on_emulation_error(CPUState *cs)
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{
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return true;
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}
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int kvm_arch_process_async_events(CPUState *cs)
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{
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return 0;
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}
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int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
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{
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return 1;
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}
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int kvm_arch_on_sigbus(int code, void *addr)
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{
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return 1;
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}
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void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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}
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int kvm_arch_insert_sw_breakpoint(CPUState *cs,
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struct kvm_sw_breakpoint *bp)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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return -EINVAL;
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}
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int kvm_arch_insert_hw_breakpoint(target_ulong addr,
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target_ulong len, int type)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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return -EINVAL;
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}
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int kvm_arch_remove_hw_breakpoint(target_ulong addr,
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target_ulong len, int type)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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return -EINVAL;
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}
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int kvm_arch_remove_sw_breakpoint(CPUState *cs,
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struct kvm_sw_breakpoint *bp)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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return -EINVAL;
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}
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void kvm_arch_remove_all_hw_breakpoints(void)
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{
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qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
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}
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