target/hppa: Implement the interval timer
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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4f5f254808
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49c29d6c2e
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@ -99,6 +99,14 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
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qemu_init_vcpu(cs);
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qemu_init_vcpu(cs);
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acc->parent_realize(dev, errp);
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acc->parent_realize(dev, errp);
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#ifndef CONFIG_USER_ONLY
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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hppa_cpu_alarm_timer, cpu);
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}
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#endif
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}
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}
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/* Sort hppabetically by type name. */
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/* Sort hppabetically by type name. */
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@ -234,6 +234,7 @@ struct HPPACPU {
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/*< public >*/
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/*< public >*/
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CPUHPPAState env;
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CPUHPPAState env;
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QEMUTimer *alarm_timer;
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};
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};
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static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
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static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
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@ -342,6 +343,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot);
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int type, hwaddr *pphys, int *pprot);
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extern const MemoryRegionOps hppa_io_eir_ops;
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extern const MemoryRegionOps hppa_io_eir_ops;
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void hppa_cpu_alarm_timer(void *);
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#endif
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#endif
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#endif /* HPPA_CPU_H */
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#endif /* HPPA_CPU_H */
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@ -77,9 +77,12 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
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DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr)
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_1(rfi, void, env)
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DEF_HELPER_1(rfi, void, env)
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DEF_HELPER_1(rfi_r, void, env)
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DEF_HELPER_1(rfi_r, void, env)
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DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr)
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DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr)
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DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr)
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DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr)
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DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr)
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DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
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DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
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@ -67,6 +67,12 @@ const MemoryRegionOps hppa_io_eir_ops = {
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.impl.max_access_size = 4,
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.impl.max_access_size = 4,
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};
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};
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void hppa_cpu_alarm_timer(void *opaque)
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{
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/* Raise interrupt 0. */
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io_eir_write(opaque, 0, 0, 4);
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}
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void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
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void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
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{
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{
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env->cr[CR_EIRR] &= ~val;
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env->cr[CR_EIRR] &= ~val;
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@ -22,6 +22,8 @@
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/timer.h"
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void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
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void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
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{
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{
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@ -602,7 +604,41 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
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return ret;
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return ret;
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}
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}
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target_ureg HELPER(read_interval_timer)(void)
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{
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#ifdef CONFIG_USER_ONLY
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/* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
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Just pass through the host cpu clock ticks. */
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return cpu_get_host_ticks();
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#else
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/* In system mode we have access to a decent high-resolution clock.
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In order to make OS-level time accounting work with the cr16,
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present it with a well-timed clock fixed at 250MHz. */
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return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2;
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
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{
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HPPACPU *cpu = hppa_env_get_cpu(env);
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uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t timeout;
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/* Even in 64-bit mode, the comparator is always 32-bit. But the
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value we expose to the guest is 1/4 of the speed of the clock,
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so moosh in 34 bits. */
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timeout = deposit64(current, 0, 34, (uint64_t)val << 2);
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/* If the mooshing puts the clock in the past, advance to next round. */
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if (timeout < current + 1000) {
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timeout += 1ULL << 34;
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}
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cpu->env.cr[CR_IT] = timeout;
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timer_mod(cpu->alarm_timer, timeout);
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}
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target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
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target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
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{
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{
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target_ulong psw = env->psw;
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target_ulong psw = env->psw;
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@ -2038,6 +2038,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn,
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unsigned rt = extract32(insn, 0, 5);
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unsigned rt = extract32(insn, 0, 5);
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unsigned ctl = extract32(insn, 21, 5);
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unsigned ctl = extract32(insn, 21, 5);
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TCGv_reg tmp;
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TCGv_reg tmp;
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DisasJumpType ret;
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switch (ctl) {
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switch (ctl) {
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case CR_SAR:
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case CR_SAR:
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@ -2056,9 +2057,17 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn,
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/* FIXME: Respect PSW_S bit. */
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/* FIXME: Respect PSW_S bit. */
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nullify_over(ctx);
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nullify_over(ctx);
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tmp = dest_gpr(ctx, rt);
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tmp = dest_gpr(ctx, rt);
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tcg_gen_movi_reg(tmp, 0); /* FIXME */
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if (ctx->base.tb->cflags & CF_USE_ICOUNT) {
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gen_io_start();
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gen_helper_read_interval_timer(tmp);
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gen_io_end();
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ret = DISAS_IAQ_N_STALE;
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} else {
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gen_helper_read_interval_timer(tmp);
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ret = DISAS_NEXT;
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}
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save_gpr(ctx, rt, tmp);
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save_gpr(ctx, rt, tmp);
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break;
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return nullify_end(ctx, ret);
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case 26:
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case 26:
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case 27:
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case 27:
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break;
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break;
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@ -2132,9 +2141,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn,
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nullify_over(ctx);
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nullify_over(ctx);
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switch (ctl) {
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switch (ctl) {
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case CR_IT:
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case CR_IT:
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/* ??? modify interval timer offset */
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gen_helper_write_interval_timer(cpu_env, reg);
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break;
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break;
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case CR_EIRR:
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case CR_EIRR:
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gen_helper_write_eirr(cpu_env, reg);
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gen_helper_write_eirr(cpu_env, reg);
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break;
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break;
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