vmxcap: correct the name of the variables
The low bits are 1 if the control must be one, the high bits are 1 if the control can be one. Correct the variable names as they are very confusing. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -51,15 +51,15 @@ class Control(object):
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return (val & 0xffffffff, val >> 32)
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def show(self):
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print(self.name)
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mbz, mb1 = self.read2(self.cap_msr)
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tmbz, tmb1 = 0, 0
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mb1, cb1 = self.read2(self.cap_msr)
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tmb1, tcb1 = 0, 0
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if self.true_cap_msr:
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tmbz, tmb1 = self.read2(self.true_cap_msr)
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tmb1, tcb1 = self.read2(self.true_cap_msr)
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for bit in sorted(self.bits.keys()):
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zero = not (mbz & (1 << bit))
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one = mb1 & (1 << bit)
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true_zero = not (tmbz & (1 << bit))
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true_one = tmb1 & (1 << bit)
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zero = not (mb1 & (1 << bit))
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one = cb1 & (1 << bit)
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true_zero = not (tmb1 & (1 << bit))
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true_one = tcb1 & (1 << bit)
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s= '?'
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if (self.true_cap_msr and true_zero and true_one
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and one and not zero):
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