target/openrisc: Rename the cpu from or32 to or1k
This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net>
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6
configure
vendored
6
configure
vendored
@ -5843,7 +5843,7 @@ target_name=$(echo $target | cut -d '-' -f 1)
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target_bigendian="no"
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case "$target_name" in
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armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
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armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
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target_bigendian=yes
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;;
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esac
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@ -5937,7 +5937,7 @@ case "$target_name" in
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;;
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nios2)
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;;
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or32)
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or1k)
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TARGET_ARCH=openrisc
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TARGET_BASE_ARCH=openrisc
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;;
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@ -6145,7 +6145,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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nios2)
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disas_config "NIOS2"
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;;
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or32)
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or1k)
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disas_config "OPENRISC"
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;;
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ppc*)
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1
default-configs/or1k-linux-user.mak
Normal file
1
default-configs/or1k-linux-user.mak
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@ -0,0 +1 @@
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# Default configuration for or1k-linux-user
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4
default-configs/or1k-softmmu.mak
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4
default-configs/or1k-softmmu.mak
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@ -0,0 +1,4 @@
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# Default configuration for or1k-softmmu
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CONFIG_SERIAL=y
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CONFIG_OPENCORES_ETH=y
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@ -1 +0,0 @@
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# Default configuration for or32-linux-user
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@ -1,4 +0,0 @@
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# Default configuration for or32-softmmu
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CONFIG_SERIAL=y
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CONFIG_OPENCORES_ETH=y
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@ -139,10 +139,10 @@ static void openrisc_sim_init(MachineState *machine)
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static void openrisc_sim_machine_init(MachineClass *mc)
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{
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mc->desc = "or32 simulation";
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mc->desc = "or1k simulation";
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mc->init = openrisc_sim_init;
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mc->max_cpus = 1;
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mc->is_default = 1;
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}
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DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init)
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DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
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@ -32,7 +32,7 @@ struct OpenRISCCPU;
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#include "fpu/softfloat.h"
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#include "qom/cpu.h"
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#define TYPE_OPENRISC_CPU "or32-cpu"
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#define TYPE_OPENRISC_CPU "or1k-cpu"
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#define OPENRISC_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
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@ -1,8 +1,8 @@
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-include ../../config-host.mak
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CROSS = or32-linux-
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CROSS = or1k-linux-
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SIM = qemu-or32
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SIM = qemu-or1k
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CC = $(CROSS)gcc
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