OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/openrisc: Rename the cpu from or32 to or1k

Browse Source 
This is in keeping with the toolchain and or1ksim.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2017-02-08 15:06:54 -08:00
parent 305e6c8a2f
commit 4a09d0bb34
8 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
configure vendored
View File

@ -5843,7 +5843,7 @@ target_name=$(echo $target | cut -d '-' -f 1)
target_bigendian="no" target_bigendian="no"
case "$target_name" in case "$target_name" in
armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
target_bigendian=yes target_bigendian=yes
;; ;;
esac esac
@ -5937,7 +5937,7 @@ case "$target_name" in
;; ;;
nios2) nios2)
;; ;;
or32) or1k)
TARGET_ARCH=openrisc TARGET_ARCH=openrisc
TARGET_BASE_ARCH=openrisc TARGET_BASE_ARCH=openrisc
;; ;;
@ -6145,7 +6145,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
nios2) nios2)
disas_config "NIOS2" disas_config "NIOS2"
;; ;;
or32) or1k)
disas_config "OPENRISC" disas_config "OPENRISC"
;; ;;
ppc*) ppc*)

1
default-configs/or1k-linux-user.mak Normal file
View File

@ -0,0 +1 @@
# Default configuration for or1k-linux-user

4
default-configs/or1k-softmmu.mak Normal file
View File

@ -0,0 +1,4 @@
# Default configuration for or1k-softmmu
CONFIG_SERIAL=y
CONFIG_OPENCORES_ETH=y

1
default-configs/or32-linux-user.mak
View File

@ -1 +0,0 @@
# Default configuration for or32-linux-user

4
default-configs/or32-softmmu.mak
View File

@ -1,4 +0,0 @@
# Default configuration for or32-softmmu
CONFIG_SERIAL=y
CONFIG_OPENCORES_ETH=y

4
hw/openrisc/openrisc_sim.c
View File

@ -139,10 +139,10 @@ static void openrisc_sim_init(MachineState *machine)
static void openrisc_sim_machine_init(MachineClass *mc) static void openrisc_sim_machine_init(MachineClass *mc)
{ {
mc->desc = "or32 simulation"; mc->desc = "or1k simulation";
mc->init = openrisc_sim_init; mc->init = openrisc_sim_init;
mc->max_cpus = 1; mc->max_cpus = 1;
mc->is_default = 1; mc->is_default = 1;
} }
DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init) DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)

2
target/openrisc/cpu.h
View File

@ -32,7 +32,7 @@ struct OpenRISCCPU;
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
#include "qom/cpu.h" #include "qom/cpu.h"
#define TYPE_OPENRISC_CPU "or32-cpu" #define TYPE_OPENRISC_CPU "or1k-cpu"
#define OPENRISC_CPU_CLASS(klass) \ #define OPENRISC_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)

4
tests/tcg/openrisc/Makefile
View File

@ -1,8 +1,8 @@
-include ../../config-host.mak -include ../../config-host.mak
CROSS = or32-linux- CROSS = or1k-linux-
SIM = qemu-or32 SIM = qemu-or1k
CC = $(CROSS)gcc CC = $(CROSS)gcc