IDE: Fix reset handling
Problem: x86 systems could not survive a few system_resets. Clear most of IDE state when reset. Implement the missing reset handlers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -193,8 +193,10 @@ static void cmd646_reset(void *opaque)
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PCIIDEState *d = opaque;
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unsigned int i;
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for (i = 0; i < 2; i++)
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ide_dma_cancel(&d->bmdma[i]);
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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ide_dma_reset(&d->bmdma[i]);
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}
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}
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/* CMD646 PCI IDE controller */
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@ -2500,17 +2500,48 @@ static void ide_dummy_transfer_stop(IDEState *s)
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s->io_buffer[3] = 0xff;
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}
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void ide_reset(IDEState *s)
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static void ide_reset(IDEState *s)
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{
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IDEBus *bus = s->bus;
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#ifdef DEBUG_IDE
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printf("ide: reset\n");
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#endif
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if (s->is_cf)
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s->mult_sectors = 0;
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else
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s->mult_sectors = MAX_MULT_SECTORS;
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bus->unit = s->unit;
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/* ide regs */
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s->feature = 0;
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s->error = 0;
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s->nsector = 0;
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s->sector = 0;
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s->lcyl = 0;
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s->hcyl = 0;
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/* lba48 */
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s->hob_feature = 0;
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s->hob_sector = 0;
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s->hob_nsector = 0;
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s->hob_lcyl = 0;
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s->hob_hcyl = 0;
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s->select = 0xa0;
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s->status = READY_STAT | SEEK_STAT;
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s->lba48 = 0;
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/* ATAPI specific */
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s->sense_key = 0;
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s->asc = 0;
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s->cdrom_changed = 0;
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s->packet_transfer_size = 0;
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s->elementary_transfer_size = 0;
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s->io_buffer_index = 0;
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s->cd_sector_size = 0;
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s->atapi_dma = 0;
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/* ATA DMA state */
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s->io_buffer_size = 0;
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s->req_nb_sectors = 0;
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ide_set_signature(s);
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/* init the transfer handler so that 0xffff is returned on data
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accesses */
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@ -2519,6 +2550,15 @@ void ide_reset(IDEState *s)
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s->media_changed = 0;
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}
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void ide_bus_reset(IDEBus *bus)
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{
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bus->unit = 0;
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bus->cmd = 0;
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ide_reset(&bus->ifs[0]);
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ide_reset(&bus->ifs[1]);
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ide_clear_hob(bus);
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}
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void ide_init_drive(IDEState *s, DriveInfo *dinfo)
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{
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int cylinders, heads, secs;
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@ -2704,3 +2744,19 @@ void ide_dma_cancel(BMDMAState *bm)
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}
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}
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void ide_dma_reset(BMDMAState *bm)
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{
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#ifdef DEBUG_IDE
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printf("ide: dma_reset\n");
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#endif
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ide_dma_cancel(bm);
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bm->cmd = 0;
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bm->status = 0;
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bm->addr = 0;
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bm->cur_addr = 0;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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bm->sector_num = 0;
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bm->nsector = 0;
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}
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@ -525,13 +525,14 @@ extern const VMStateDescription vmstate_ide_drive;
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#define VMSTATE_IDE_DRIVES(_field, _state) \
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VMSTATE_STRUCT_ARRAY(_field, _state, 2, 3, vmstate_ide_drive, IDEState)
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void ide_reset(IDEState *s);
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void ide_bus_reset(IDEBus *bus);
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int64_t ide_get_sector(IDEState *s);
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void ide_set_sector(IDEState *s, int64_t sector_num);
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void ide_dma_cancel(BMDMAState *bm);
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void ide_dma_restart_cb(void *opaque, int running, int reason);
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void ide_dma_error(IDEState *s);
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void ide_dma_reset(BMDMAState *bm);
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void ide_atapi_cmd_ok(IDEState *s);
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void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc);
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@ -44,6 +44,13 @@ typedef struct ISAIDEState {
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qemu_irq irq;
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} ISAIDEState;
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static void isa_ide_reset(DeviceState *d)
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{
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ISAIDEState *s = container_of(d, ISAIDEState, dev.qdev);
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ide_bus_reset(&s->bus);
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}
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static const VMStateDescription vmstate_ide_isa = {
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.name = "isa-ide",
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.version_id = 3,
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@ -93,6 +100,7 @@ static ISADeviceInfo isa_ide_info = {
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.qdev.name = "isa-ide",
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.qdev.size = sizeof(ISAIDEState),
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.init = isa_ide_initfn,
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.qdev.reset = isa_ide_reset,
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.qdev.props = (Property[]) {
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DEFINE_PROP_HEX32("iobase", ISAIDEState, iobase, 0x1f0),
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DEFINE_PROP_HEX32("iobase2", ISAIDEState, iobase2, 0x3f6),
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@ -307,8 +307,7 @@ static void pmac_ide_reset(void *opaque)
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{
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MACIOIDEState *d = opaque;
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ide_reset(d->bus.ifs +0);
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ide_reset(d->bus.ifs +1);
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ide_bus_reset(&d->bus);
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}
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/* hd_table must contain 4 block drivers */
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@ -110,7 +110,7 @@ static void md_reset(MicroDriveState *s)
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s->pins = 0;
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s->cycle = 0;
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s->ctrl = 0;
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ide_reset(s->bus.ifs);
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ide_bus_reset(&s->bus);
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}
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static uint8_t md_attr_read(void *opaque, uint32_t at)
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@ -41,6 +41,13 @@ typedef struct {
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int shift;
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} MMIOState;
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static void mmio_ide_reset(void *opaque)
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{
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MMIOState *s = opaque;
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ide_bus_reset(&s->bus);
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}
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static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
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{
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MMIOState *s = opaque;
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@ -127,5 +134,6 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
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cpu_register_physical_memory(membase, 16 << shift, mem1);
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cpu_register_physical_memory(membase2, 2 << shift, mem2);
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vmstate_register(0, &vmstate_ide_mmio, s);
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qemu_register_reset(mmio_ide_reset, s);
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}
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@ -101,8 +101,10 @@ static void piix3_reset(void *opaque)
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uint8_t *pci_conf = d->dev.config;
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int i;
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for (i = 0; i < 2; i++)
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ide_dma_cancel(&d->bmdma[i]);
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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ide_dma_reset(&d->bmdma[i]);
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}
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pci_conf[0x04] = 0x00;
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pci_conf[0x05] = 0x00;
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