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target/arm: Make rvbar settable after realize 

Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2022-03-16 17:46:41 +01:00 committed by Peter Maydell
parent c28d4b8656
commit 4a7319b750
3 changed files with 16 additions and 9 deletions
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12
target/arm/cpu.c
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@ -236,7 +236,10 @@ static void arm_cpu_reset(DeviceState *dev)
} else { } else {
env->pstate = PSTATE_MODE_EL1h; env->pstate = PSTATE_MODE_EL1h;
} }
env->pc = cpu->rvbar;
/* Sample rvbar at reset. */
env->cp15.rvbar = cpu->rvbar_prop;
env->pc = env->cp15.rvbar;
#endif #endif
} else { } else {
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -1135,9 +1138,6 @@ static Property arm_cpu_reset_cbar_property =
static Property arm_cpu_reset_hivecs_property = static Property arm_cpu_reset_hivecs_property =
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
static Property arm_cpu_rvbar_property =
DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static Property arm_cpu_has_el2_property = static Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
@ -1240,7 +1240,9 @@ void arm_cpu_post_init(Object *obj)
} }
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); object_property_add_uint64_ptr(obj, "rvbar",
&cpu->rvbar_prop,
OBJ_PROP_FLAG_READWRITE);
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY

3
target/arm/cpu.h
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@ -447,6 +447,7 @@ typedef struct CPUArchState {
uint64_t vbar_el[4]; uint64_t vbar_el[4];
}; };
uint32_t mvbar; /* (monitor) vector base address register */ uint32_t mvbar; /* (monitor) vector base address register */
uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
struct { /* FCSE PID. */ struct { /* FCSE PID. */
uint32_t fcseidr_ns; uint32_t fcseidr_ns;
uint32_t fcseidr_s; uint32_t fcseidr_s;
@ -985,7 +986,7 @@ struct ArchCPU {
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
uint32_t dcz_blocksize; uint32_t dcz_blocksize;
uint64_t rvbar; uint64_t rvbar_prop; /* Property/input signals. */
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
int gic_num_lrs; /* number of list registers */ int gic_num_lrs; /* number of list registers */

10
target/arm/helper.c
View File

@ -7967,7 +7967,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo rvbar = { ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar .access = PL1_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
}; };
define_one_arm_cp_reg(cpu, &rvbar); define_one_arm_cp_reg(cpu, &rvbar);
} }
@ -8011,7 +8012,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo rvbar = { ARMCPRegInfo rvbar = {
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar .access = PL2_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
}; };
define_one_arm_cp_reg(cpu, &rvbar); define_one_arm_cp_reg(cpu, &rvbar);
} }
@ -8048,7 +8050,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo el3_regs[] = { ARMCPRegInfo el3_regs[] = {
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, .access = PL3_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
},
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW, .access = PL3_RW,