target/riscv: vector single-width floating-point fused multiply-add instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-35-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
f7c7b7cd29
commit
4aa5a8fed4
@ -857,3 +857,52 @@ DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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@ -465,6 +465,22 @@ vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
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vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
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vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
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vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
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vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
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vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
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vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
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vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
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vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
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vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
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vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
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vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
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vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
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vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
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vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
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vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
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vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
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vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
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vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
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vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -2061,3 +2061,21 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
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/* Vector Widening Floating-Point Multiply */
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GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
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GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
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/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
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GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
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GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
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GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
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@ -3432,3 +3432,254 @@ RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
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RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
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GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
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GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)
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/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
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#define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
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static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
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CPURISCVState *env) \
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{ \
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TX1 s1 = *((T1 *)vs1 + HS1(i)); \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(s2, s1, d, &env->fp_status); \
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}
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static uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
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{
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return float16_muladd(a, b, d, 0, s);
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}
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static uint32_t fmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
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{
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return float32_muladd(a, b, d, 0, s);
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}
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static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
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{
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return float64_muladd(a, b, d, 0, s);
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}
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RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
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RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
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RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
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GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2, clearh)
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GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4, clearl)
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GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8, clearq)
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#define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
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static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
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CPURISCVState *env) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d, &env->fp_status);\
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}
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RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
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RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
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RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
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GEN_VEXT_VF(vfmacc_vf_h, 2, 2, clearh)
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GEN_VEXT_VF(vfmacc_vf_w, 4, 4, clearl)
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GEN_VEXT_VF(vfmacc_vf_d, 8, 8, clearq)
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static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
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{
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return float16_muladd(a, b, d,
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float_muladd_negate_c | float_muladd_negate_product, s);
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}
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static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
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{
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return float32_muladd(a, b, d,
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float_muladd_negate_c | float_muladd_negate_product, s);
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}
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static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
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{
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return float64_muladd(a, b, d,
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float_muladd_negate_c | float_muladd_negate_product, s);
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}
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RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
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RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
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RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
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GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2, clearh)
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GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4, clearl)
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GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8, clearq)
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RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
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RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
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RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
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GEN_VEXT_VF(vfnmacc_vf_h, 2, 2, clearh)
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GEN_VEXT_VF(vfnmacc_vf_w, 4, 4, clearl)
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GEN_VEXT_VF(vfnmacc_vf_d, 8, 8, clearq)
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static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
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{
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return float16_muladd(a, b, d, float_muladd_negate_c, s);
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}
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static uint32_t fmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
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{
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return float32_muladd(a, b, d, float_muladd_negate_c, s);
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}
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static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
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{
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return float64_muladd(a, b, d, float_muladd_negate_c, s);
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}
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RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
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RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
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RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
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GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2, clearh)
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GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4, clearl)
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GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8, clearq)
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RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
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RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
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RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
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GEN_VEXT_VF(vfmsac_vf_h, 2, 2, clearh)
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GEN_VEXT_VF(vfmsac_vf_w, 4, 4, clearl)
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GEN_VEXT_VF(vfmsac_vf_d, 8, 8, clearq)
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static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
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{
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return float16_muladd(a, b, d, float_muladd_negate_product, s);
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}
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static uint32_t fnmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
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{
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return float32_muladd(a, b, d, float_muladd_negate_product, s);
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}
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static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
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{
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return float64_muladd(a, b, d, float_muladd_negate_product, s);
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}
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RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
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RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
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RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
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GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2, clearh)
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GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4, clearl)
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GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8, clearq)
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RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
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RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
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RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
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GEN_VEXT_VF(vfnmsac_vf_h, 2, 2, clearh)
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GEN_VEXT_VF(vfnmsac_vf_w, 4, 4, clearl)
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GEN_VEXT_VF(vfnmsac_vf_d, 8, 8, clearq)
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static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
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{
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return float16_muladd(d, b, a, 0, s);
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}
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static uint32_t fmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
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{
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return float32_muladd(d, b, a, 0, s);
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}
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static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
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{
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return float64_muladd(d, b, a, 0, s);
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}
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RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
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RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
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RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
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GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2, clearh)
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GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4, clearl)
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GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8, clearq)
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RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
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RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
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RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
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GEN_VEXT_VF(vfmadd_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfmadd_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfmadd_vf_d, 8, 8, clearq)
|
||||
|
||||
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
|
||||
{
|
||||
return float16_muladd(d, b, a,
|
||||
float_muladd_negate_c | float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
|
||||
{
|
||||
return float32_muladd(d, b, a,
|
||||
float_muladd_negate_c | float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
|
||||
{
|
||||
return float64_muladd(d, b, a,
|
||||
float_muladd_negate_c | float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
|
||||
RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
|
||||
RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
|
||||
GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2, clearh)
|
||||
GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4, clearl)
|
||||
GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8, clearq)
|
||||
RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
|
||||
RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
|
||||
RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
|
||||
GEN_VEXT_VF(vfnmadd_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfnmadd_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfnmadd_vf_d, 8, 8, clearq)
|
||||
|
||||
static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
|
||||
{
|
||||
return float16_muladd(d, b, a, float_muladd_negate_c, s);
|
||||
}
|
||||
|
||||
static uint32_t fmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
|
||||
{
|
||||
return float32_muladd(d, b, a, float_muladd_negate_c, s);
|
||||
}
|
||||
|
||||
static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
|
||||
{
|
||||
return float64_muladd(d, b, a, float_muladd_negate_c, s);
|
||||
}
|
||||
|
||||
RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
|
||||
RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
|
||||
RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
|
||||
GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2, clearh)
|
||||
GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4, clearl)
|
||||
GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8, clearq)
|
||||
RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
|
||||
RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
|
||||
RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
|
||||
GEN_VEXT_VF(vfmsub_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfmsub_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfmsub_vf_d, 8, 8, clearq)
|
||||
|
||||
static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
|
||||
{
|
||||
return float16_muladd(d, b, a, float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
static uint32_t fnmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
|
||||
{
|
||||
return float32_muladd(d, b, a, float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
|
||||
{
|
||||
return float64_muladd(d, b, a, float_muladd_negate_product, s);
|
||||
}
|
||||
|
||||
RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
|
||||
RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
|
||||
RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
|
||||
GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2, clearh)
|
||||
GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4, clearl)
|
||||
GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8, clearq)
|
||||
RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
|
||||
RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
|
||||
RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
|
||||
GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user