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Add cirrus reset handler

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The vga reset handler overwrites some cirrus registers, causing reboots
to corrupt cirrus state to the point that guests can only bring up 640x480
resolutions.

Fix by adding a dedicated cirrus reset handler (which calls the common vga
handler).

Signed-off-by: Avi Kivity <avi@redhat.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6191 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2009-01-05 17:37:06 +00:00
parent 785f451b62
commit 4abc796d41
3 changed files with 66 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
hw/cirrus_vga.c
View File

@ -287,6 +287,8 @@ typedef struct CirrusVGAState {
int last_hw_cursor_y_end; int last_hw_cursor_y_end;
int real_vram_size; /* XXX: suppress that */ int real_vram_size; /* XXX: suppress that */
CPUWriteMemoryFunc **cirrus_linear_write; CPUWriteMemoryFunc **cirrus_linear_write;
int device_id;
int bustype;
} CirrusVGAState; } CirrusVGAState;
typedef struct PCICirrusVGAState { typedef struct PCICirrusVGAState {
@ -3175,55 +3177,13 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
* *
***************************************/ ***************************************/
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) static void cirrus_reset(void *opaque)
{ {
int i; CirrusVGAState *s = opaque;
static int inited;
if (!inited) {
inited = 1;
for(i = 0;i < 256; i++)
rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
rop_to_index[CIRRUS_ROP_0] = 0;
rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
rop_to_index[CIRRUS_ROP_NOP] = 2;
rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
rop_to_index[CIRRUS_ROP_NOTDST] = 4;
rop_to_index[CIRRUS_ROP_SRC] = 5;
rop_to_index[CIRRUS_ROP_1] = 6;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
}
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
cirrus_vga_mem_write, s);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
s->vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
vga_reset(s);
s->sr[0x06] = 0x0f; s->sr[0x06] = 0x0f;
if (device_id == CIRRUS_ID_CLGD5446) { if (s->device_id == CIRRUS_ID_CLGD5446) {
/* 4MB 64 bit memory config, always PCI */ /* 4MB 64 bit memory config, always PCI */
s->sr[0x1F] = 0x2d; // MemClock s->sr[0x1F] = 0x2d; // MemClock
s->gr[0x18] = 0x0f; // fastest memory configuration s->gr[0x18] = 0x0f; // fastest memory configuration
@ -3241,14 +3201,11 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
} else { } else {
s->sr[0x1F] = 0x22; // MemClock s->sr[0x1F] = 0x22; // MemClock
s->sr[0x0F] = CIRRUS_MEMSIZE_2M; s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
if (is_pci) s->sr[0x17] = s->bustype;
s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
else
s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
s->real_vram_size = 2048 * 1024; s->real_vram_size = 2048 * 1024;
s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
} }
s->cr[0x27] = device_id; s->cr[0x27] = s->device_id;
/* Win2K seems to assume that the pattern buffer is at 0xff /* Win2K seems to assume that the pattern buffer is at 0xff
initially ! */ initially ! */
@ -3281,7 +3238,62 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
s->get_resolution = cirrus_get_resolution; s->get_resolution = cirrus_get_resolution;
s->cursor_invalidate = cirrus_cursor_invalidate; s->cursor_invalidate = cirrus_cursor_invalidate;
s->cursor_draw_line = cirrus_cursor_draw_line; s->cursor_draw_line = cirrus_cursor_draw_line;
}
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
{
int i;
static int inited;
if (!inited) {
inited = 1;
for(i = 0;i < 256; i++)
rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
rop_to_index[CIRRUS_ROP_0] = 0;
rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
rop_to_index[CIRRUS_ROP_NOP] = 2;
rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
rop_to_index[CIRRUS_ROP_NOTDST] = 4;
rop_to_index[CIRRUS_ROP_SRC] = 5;
rop_to_index[CIRRUS_ROP_1] = 6;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
s->device_id = device_id;
if (is_pci)
s->bustype = CIRRUS_BUSTYPE_PCI;
else
s->bustype = CIRRUS_BUSTYPE_ISA;
}
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
cirrus_vga_mem_write, s);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
s->vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
qemu_register_reset(cirrus_reset, s);
cirrus_reset(s);
register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s); register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
} }

4
hw/vga.c
View File

@ -1839,7 +1839,7 @@ static void vga_invalidate_display(void *opaque)
s->last_height = -1; s->last_height = -1;
} }
static void vga_reset(void *opaque) void vga_reset(void *opaque)
{ {
VGAState *s = (VGAState *) opaque; VGAState *s = (VGAState *) opaque;
@ -2277,7 +2277,6 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
s->update_retrace_info = vga_precise_update_retrace_info; s->update_retrace_info = vga_precise_update_retrace_info;
break; break;
} }
qemu_register_reset(vga_reset, s);
vga_reset(s); vga_reset(s);
} }
@ -2286,6 +2285,7 @@ void vga_init(VGAState *s)
{ {
int vga_io_memory; int vga_io_memory;
qemu_register_reset(vga_reset, s);
register_savevm("vga", 0, 2, vga_save, vga_load, s); register_savevm("vga", 0, 2, vga_save, vga_load, s);
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);

1
hw/vga_int.h
View File

@ -193,6 +193,7 @@ static inline int c6_to_8(int v)
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base, void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size); ram_addr_t vga_ram_offset, int vga_ram_size);
void vga_init(VGAState *s); void vga_init(VGAState *s);
void vga_reset(void *s);
void vga_dirty_log_start(VGAState *s); void vga_dirty_log_start(VGAState *s);
void vga_dirty_log_stop(VGAState *s); void vga_dirty_log_stop(VGAState *s);