fix spelling in target sub directory

Cc: Richard Henderson <rth@twiddle.net>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
This commit is contained in:
Dong Xu Wang 2011-11-22 18:06:21 +08:00 committed by Stefan Hajnoczi
parent 68dfbcd4d5
commit 4abf79a428
10 changed files with 13 additions and 13 deletions

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@ -18,7 +18,7 @@ Linux user mode emulation status:
a few programs start to run. Most crash at a certain point, dereferencing a a few programs start to run. Most crash at a certain point, dereferencing a
NULL pointer. It seems that the UNIQUE register is not initialized properly. NULL pointer. It seems that the UNIQUE register is not initialized properly.
It may appear that old executables, not relying on TLS support, run but It may appear that old executables, not relying on TLS support, run but
this is to be prooved... this is to be proved...
Full system emulation status: Full system emulation status:
* Alpha PALCode emulation is in a very early stage and is not sufficient * Alpha PALCode emulation is in a very early stage and is not sufficient

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@ -243,7 +243,7 @@ typedef struct CPUMBState {
#define DRTE_FLAG (1 << 17) #define DRTE_FLAG (1 << 17)
#define DRTB_FLAG (1 << 18) #define DRTB_FLAG (1 << 18)
#define D_FLAG (1 << 19) /* Bit in ESR. */ #define D_FLAG (1 << 19) /* Bit in ESR. */
/* TB dependant CPUState. */ /* TB dependent CPUState. */
#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags; uint32_t iflags;

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@ -120,7 +120,7 @@ static inline int sign_extend(unsigned int val, unsigned int width)
static inline void t_sync_flags(DisasContext *dc) static inline void t_sync_flags(DisasContext *dc)
{ {
/* Synch the tb dependant flags between translator and runtime. */ /* Synch the tb dependent flags between translator and runtime. */
if (dc->tb_flags != dc->synced_flags) { if (dc->tb_flags != dc->synced_flags) {
tcg_gen_movi_tl(env_iflags, dc->tb_flags); tcg_gen_movi_tl(env_iflags, dc->tb_flags);
dc->synced_flags = dc->tb_flags; dc->synced_flags = dc->tb_flags;
@ -1122,7 +1122,7 @@ static void dec_store(DisasContext *dc)
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
/* FIXME: if the alignment is wrong, we should restore the value /* FIXME: if the alignment is wrong, we should restore the value
* in memory. One possible way to acheive this is to probe * in memory. One possible way to achieve this is to probe
* the MMU prior to the memaccess, thay way we could put * the MMU prior to the memaccess, thay way we could put
* the alignment checks in between the probe and the mem * the alignment checks in between the probe and the mem
* access. * access.

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@ -678,7 +678,7 @@ static inline int mips_vpe_active(CPUState *env)
if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
active = 0; active = 0;
} }
/* Check that the VPE is actived. */ /* Check that the VPE is activated. */
if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
active = 0; active = 0;
} }

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@ -302,7 +302,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < MIPS_FPU_MAX; i++) for (i = 0; i < MIPS_FPU_MAX; i++)
load_fpu(f, &env->fpus[i]); load_fpu(f, &env->fpus[i]);
/* XXX: ensure compatiblity for halted bit ? */ /* XXX: ensure compatibility for halted bit ? */
tlb_flush(env, 1); tlb_flush(env, 1);
return 0; return 0;
} }

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@ -1004,7 +1004,7 @@ struct CPUPPCState {
int error_code; int error_code;
uint32_t pending_interrupts; uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant /* This is the IRQ controller, which is implementation dependent
* and only relevant when emulating a complete machine. * and only relevant when emulating a complete machine.
*/ */
uint32_t irq_input_state; uint32_t irq_input_state;
@ -1024,7 +1024,7 @@ struct CPUPPCState {
/* Those resources are used only in Qemu core */ /* Those resources are used only in Qemu core */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */ target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */ int mmu_idx; /* precomputed MMU index to speed up mem accesses */
/* Power management */ /* Power management */

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@ -11,7 +11,7 @@ int main (void)
printf("static const uint8_t mfrom_ROM_table[602] =\n{\n "); printf("static const uint8_t mfrom_ROM_table[602] =\n{\n ");
for (i = 0; i < 602; i++) { for (i = 0; i < 602; i++) {
/* Extremly decomposed: /* Extremely decomposed:
* -T0 / 256 * -T0 / 256
* T0 = 256 * log10(10 + 1.0) + 0.5 * T0 = 256 * log10(10 + 1.0) + 0.5
*/ */

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@ -1795,7 +1795,7 @@ void helper_rfsvc (void)
/* 602 specific instructions */ /* 602 specific instructions */
/* mfrom is the most crazy instruction ever seen, imho ! */ /* mfrom is the most crazy instruction ever seen, imho ! */
/* Real implementation uses a ROM table. Do the same */ /* Real implementation uses a ROM table. Do the same */
/* Extremly decomposed: /* Extremely decomposed:
* -arg / 256 * -arg / 256
* return 256 * log10(10 + 1.0) + 0.5 * return 256 * log10(10 + 1.0) + 0.5
*/ */
@ -3070,7 +3070,7 @@ static inline uint32_t word_reverse(uint32_t val)
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
} }
#define MASKBITS 16 // Random value - to be fixed (implementation dependant) #define MASKBITS 16 // Random value - to be fixed (implementation dependent)
target_ulong helper_brinc (target_ulong arg1, target_ulong arg2) target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
{ {
uint32_t a, b, d, mask; uint32_t a, b, d, mask;

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@ -814,7 +814,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
/* /*
* TODO : Evaluate CCR and check if the cache is on or off. * TODO : Evaluate CCR and check if the cache is on or off.
* Now CCR is not in CPUSH4State, but in SH7750State. * Now CCR is not in CPUSH4State, but in SH7750State.
* When you move the ccr inot CPUSH4State, the code will be * When you move the ccr into CPUSH4State, the code will be
* as follows. * as follows.
*/ */
#if 0 #if 0

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@ -15,7 +15,7 @@ CPU common:
- NPC/PC static optimisations (use JUMP_TB when possible)? (Is this - NPC/PC static optimisations (use JUMP_TB when possible)? (Is this
obsolete?) obsolete?)
- Synthetic instructions - Synthetic instructions
- MMU model dependant on CPU model - MMU model dependent on CPU model
- Select ASI helper at translation time (on V9 only if known) - Select ASI helper at translation time (on V9 only if known)
- KQemu/KVM support for VM only - KQemu/KVM support for VM only
- Hardware breakpoint/watchpoint support - Hardware breakpoint/watchpoint support