M48T02 support (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3872 c046a42c-6fe2-441c-8c8c-71466251a162
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blueswir1
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51
hw/m48t59.c
51
hw/m48t59.c
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@ -36,13 +36,13 @@
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#endif
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/*
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* The M48T08 and M48T59 chips are very similar. The newer '59 has
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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struct m48t59_t {
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/* Model parameters */
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int type; // 8 = m48t08, 59 = m48t59
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int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
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/* Hardware parameters */
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qemu_irq IRQ;
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int mem_index;
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@ -210,9 +210,14 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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if (NVRAM->type == 8 &&
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(addr >= 0x1ff0 && addr <= 0x1ff7))
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x7f8) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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goto do_write;
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register : read-only */
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@ -270,10 +275,12 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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set_up_watchdog(NVRAM, val);
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break;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
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break;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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@ -281,7 +288,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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tm.tm_sec = tmp;
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set_time(NVRAM, &tm);
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}
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if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
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if (val & 0x80) {
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NVRAM->stop_time = time(NULL);
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} else {
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@ -289,9 +296,10 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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NVRAM->stop_time = 0;
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}
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}
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NVRAM->buffer[0x1FF9] = val & 0x80;
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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@ -301,6 +309,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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}
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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@ -310,14 +319,16 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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}
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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tmp = fromBCD(val & 0x07);
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get_time(NVRAM, &tm);
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tm.tm_wday = tmp;
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set_time(NVRAM, &tm);
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NVRAM->buffer[0x1FFC] = val & 0x40;
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NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) {
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@ -327,6 +338,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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}
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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tmp = fromBCD(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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@ -336,6 +348,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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}
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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tmp = fromBCD(val);
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if (tmp >= 0 && tmp <= 99) {
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@ -367,9 +380,13 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
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struct tm tm;
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uint32_t retval = 0xFF;
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if (NVRAM->type == 8 &&
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(addr >= 0x1ff0 && addr <= 0x1ff7))
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x078f) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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goto do_read;
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register */
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@ -398,39 +415,47 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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goto do_read;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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goto do_read;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
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retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_min);
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_hour);
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
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retval = NVRAM->buffer[addr] | tm.tm_wday;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_mday);
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_mon + 1);
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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get_time(NVRAM, &tm);
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if (NVRAM->type == 8)
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@ -650,7 +675,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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}
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if (mem_base != 0) {
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s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
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cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
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cpu_register_physical_memory(mem_base, size, s->mem_index);
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}
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if (type == 59) {
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s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
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@ -623,7 +623,7 @@ static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
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}
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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hwdef->nvram_size, 2);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
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nographic);
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@ -848,7 +848,7 @@ static const struct hwdef hwdefs[] = {
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.sun4c_intctl_base = 0xf5000000,
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.sun4c_counter_base = 0xf3000000,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000, // XXX 0x800,
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.nvram_size = 0x800,
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.esp_irq = 2,
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.le_irq = 3,
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.clock_irq = 5,
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