OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Optimize MVE 1op-immediate insns

Browse Source 
Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to
use TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-13-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-09-13 10:54:40 +01:00
parent ce75c43f6d
commit 4b445c926a
1 changed files with 21 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
target/arm/translate-mve.c
View File

@ -1521,7 +1521,8 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
return true; return true;
} }
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,
GVecGen2iFn *vecfn)
{ {
TCGv_ptr qd; TCGv_ptr qd;
uint64_t imm; uint64_t imm;
@ -1537,17 +1538,29 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
imm = asimd_imm_const(a->imm, a->cmode, a->op); imm = asimd_imm_const(a->imm, a->cmode, a->op);
qd = mve_qreg_ptr(a->qd); if (vecfn && mve_no_predication(s)) {
fn(cpu_env, qd, tcg_constant_i64(imm)); vecfn(MO_64, mve_qreg_offset(a->qd), mve_qreg_offset(a->qd),
tcg_temp_free_ptr(qd); imm, 16, 16);
} else {
qd = mve_qreg_ptr(a->qd);
fn(cpu_env, qd, tcg_constant_i64(imm));
tcg_temp_free_ptr(qd);
}
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
static void gen_gvec_vmovi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c);
}
static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
{ {
/* Handle decode of cmode/op here between VORR/VBIC/VMOV */ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
MVEGenOneOpImmFn *fn; MVEGenOneOpImmFn *fn;
GVecGen2iFn *vecfn;
if ((a->cmode & 1) && a->cmode < 12) { if ((a->cmode & 1) && a->cmode < 12) {
if (a->op) { if (a->op) {
@ -1556,8 +1569,10 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
* so the VBIC becomes a logical AND operation. * so the VBIC becomes a logical AND operation.
*/ */
fn = gen_helper_mve_vandi; fn = gen_helper_mve_vandi;
vecfn = tcg_gen_gvec_andi;
} else { } else {
fn = gen_helper_mve_vorri; fn = gen_helper_mve_vorri;
vecfn = tcg_gen_gvec_ori;
} }
} else { } else {
/* There is one unallocated cmode/op combination in this space */ /* There is one unallocated cmode/op combination in this space */
@ -1566,8 +1581,9 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
} }
/* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
fn = gen_helper_mve_vmovi; fn = gen_helper_mve_vmovi;
vecfn = gen_gvec_vmovi;
} }
return do_1imm(s, a, fn); return do_1imm(s, a, fn, vecfn);
} }
static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,