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riscv: sifive_u: Update UART base addresses and IRQs

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This updates the UART base address and IRQs to match the hardware.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jonathan Behrens <fintelia@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:20:12 -07:00 committed by Palmer Dabbelt
parent 806c64b7b0
commit 4b55bc2b5f
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GPG Key ID: EF4CA1502CCBAB41
2 changed files with 4 additions and 4 deletions
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4
hw/riscv/sifive_u.c
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@ -62,8 +62,8 @@ static const struct MemmapEntry {
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};

4
include/hw/riscv/sifive_u.h
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@ -65,8 +65,8 @@ enum {
};
enum {
SIFIVE_U_UART0_IRQ = 3,
SIFIVE_U_UART1_IRQ = 4,
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GEM_IRQ = 0x35
};