Merge branch 'tcg-s390' of git://github.com/rth7680/qemu
* 'tcg-s390' of git://github.com/rth7680/qemu: tcg-s390: Fix merge error in tgen_brcond tcg-s390: Use all 20 bits of the offset in tcg_out_mem tcg-s390: Use load-address for addition tcg-s390: Cleanup argument shuffling fixme in softmmu code tcg-s390: Use risbgz for andi tcg-s390: Remove constraint letters for and tcg-s390: Implement deposit opcodes tcg-s390: Implement movcond opcodes tcg-s390: Implement mulu2_i64 opcode tcg-s390: Implement add2/sub2 opcodes tcg-s390: Remove useless preprocessor conditions tcg-s390: Properly allocate a stack frame. tcg-s390: Fix movi
This commit is contained in:
Aurelien Jarno
commit
4b7b054682
@ -24,16 +24,18 @@
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* THE SOFTWARE.
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*/
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/* We only support generating code for 64-bit mode. */
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#if TCG_TARGET_REG_BITS != 64
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#error "unsupported code generation mode"
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#endif
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/* ??? The translation blocks produced by TCG are generally small enough to
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be entirely reachable with a 16-bit displacement. Leaving the option for
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a 32-bit displacement here Just In Case. */
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#define USE_LONG_BRANCHES 0
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#define TCG_CT_CONST_32 0x0100
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#define TCG_CT_CONST_NEG 0x0200
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#define TCG_CT_CONST_ADDI 0x0400
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#define TCG_CT_CONST_MULI 0x0800
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#define TCG_CT_CONST_ANDI 0x1000
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#define TCG_CT_CONST_ORI 0x2000
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#define TCG_CT_CONST_XORI 0x4000
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#define TCG_CT_CONST_CMPI 0x8000
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@ -63,6 +65,7 @@
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typedef enum S390Opcode {
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RIL_AFI = 0xc209,
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RIL_AGFI = 0xc208,
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RIL_ALFI = 0xc20b,
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RIL_ALGFI = 0xc20a,
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RIL_BRASL = 0xc005,
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RIL_BRCL = 0xc004,
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@ -84,6 +87,8 @@ typedef enum S390Opcode {
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RIL_NILF = 0xc00b,
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RIL_OIHF = 0xc00c,
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RIL_OILF = 0xc00d,
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RIL_SLFI = 0xc205,
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RIL_SLGFI = 0xc204,
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RIL_XIHF = 0xc006,
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RIL_XILF = 0xc007,
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@ -118,8 +123,12 @@ typedef enum S390Opcode {
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RIE_CLGIJ = 0xec7d,
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RIE_CLRJ = 0xec77,
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RIE_CRJ = 0xec76,
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RIE_RISBG = 0xec55,
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RRE_AGR = 0xb908,
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RRE_ALGR = 0xb90a,
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RRE_ALCR = 0xb998,
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RRE_ALCGR = 0xb988,
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RRE_CGR = 0xb920,
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RRE_CLGR = 0xb921,
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RRE_DLGR = 0xb987,
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@ -137,14 +146,22 @@ typedef enum S390Opcode {
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RRE_LRVR = 0xb91f,
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RRE_LRVGR = 0xb90f,
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RRE_LTGR = 0xb902,
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RRE_MLGR = 0xb986,
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RRE_MSGR = 0xb90c,
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RRE_MSR = 0xb252,
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RRE_NGR = 0xb980,
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RRE_OGR = 0xb981,
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RRE_SGR = 0xb909,
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RRE_SLGR = 0xb90b,
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RRE_SLBR = 0xb999,
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RRE_SLBGR = 0xb989,
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RRE_XGR = 0xb982,
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RRF_LOCR = 0xb9f2,
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RRF_LOCGR = 0xb9e2,
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RR_AR = 0x1a,
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RR_ALR = 0x1e,
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RR_BASR = 0x0d,
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RR_BCR = 0x07,
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RR_CLR = 0x15,
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@ -156,6 +173,7 @@ typedef enum S390Opcode {
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RR_NR = 0x14,
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RR_OR = 0x16,
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RR_SR = 0x1b,
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RR_SLR = 0x1f,
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RR_XR = 0x17,
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RSY_RLL = 0xeb1d,
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@ -172,6 +190,7 @@ typedef enum S390Opcode {
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RXY_AY = 0xe35a,
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RXY_CG = 0xe320,
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RXY_CY = 0xe359,
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RXY_LAY = 0xe371,
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RXY_LB = 0xe376,
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RXY_LG = 0xe304,
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RXY_LGB = 0xe377,
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@ -198,6 +217,7 @@ typedef enum S390Opcode {
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RX_A = 0x5a,
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RX_C = 0x59,
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RX_L = 0x58,
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RX_LA = 0x41,
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RX_LH = 0x48,
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RX_ST = 0x50,
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RX_STC = 0x42,
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@ -252,9 +272,6 @@ static const int tcg_target_call_iarg_regs[] = {
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static const int tcg_target_call_oarg_regs[] = {
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TCG_REG_R2,
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#if TCG_TARGET_REG_BITS == 32
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TCG_REG_R3
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#endif
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};
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#define S390_CC_EQ 8
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@ -329,6 +346,7 @@ static uint8_t *tb_ret_addr;
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#define FACILITY_LONG_DISP (1ULL << (63 - 18))
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#define FACILITY_EXT_IMM (1ULL << (63 - 21))
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#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
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#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
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static uint64_t facilities;
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@ -376,6 +394,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set32(ct->u.regs, 0, 0xffff);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
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break;
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case 'a': /* force R2 for division */
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ct->ct |= TCG_CT_REG;
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@ -387,21 +406,12 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_clear(ct->u.regs);
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tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
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break;
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case 'N': /* force immediate negate */
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ct->ct |= TCG_CT_CONST_NEG;
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break;
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case 'W': /* force 32-bit ("word") immediate */
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ct->ct |= TCG_CT_CONST_32;
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_ADDI;
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break;
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case 'K':
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ct->ct |= TCG_CT_CONST_MULI;
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break;
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case 'A':
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ct->ct |= TCG_CT_CONST_ANDI;
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break;
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case 'O':
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ct->ct |= TCG_CT_CONST_ORI;
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break;
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@ -420,63 +430,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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return 0;
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}
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/* Immediates to be used with logical AND. This is an optimization only,
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since a full 64-bit immediate AND can always be performed with 4 sequential
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NI[LH][LH] instructions. What we're looking for is immediates that we
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can load efficiently, and the immediate load plus the reg-reg AND is
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smaller than the sequential NI's. */
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static int tcg_match_andi(int ct, tcg_target_ulong val)
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{
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int i;
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if (facilities & FACILITY_EXT_IMM) {
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if (ct & TCG_CT_CONST_32) {
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/* All 32-bit ANDs can be performed with 1 48-bit insn. */
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return 1;
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}
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/* Zero-extensions. */
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if (val == 0xff || val == 0xffff || val == 0xffffffff) {
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return 1;
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}
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} else {
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if (ct & TCG_CT_CONST_32) {
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val = (uint32_t)val;
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} else if (val == 0xffffffff) {
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return 1;
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}
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}
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/* Try all 32-bit insns that can perform it in one go. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = ~(0xffffull << i*16);
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if ((val & mask) == mask) {
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return 1;
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}
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}
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/* Look for 16-bit values performing the mask. These are better
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to load with LLI[LH][LH]. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = 0xffffull << i*16;
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if ((val & mask) == val) {
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return 0;
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}
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}
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/* Look for 32-bit values performing the 64-bit mask. These
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are better to load with LLI[LH]F, or if extended immediates
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not available, with a pair of LLI insns. */
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if ((ct & TCG_CT_CONST_32) == 0) {
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if (val <= 0xffffffff || (val & 0xffffffff) == 0) {
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return 0;
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}
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}
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return 1;
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}
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/* Immediates to be used with logical OR. This is an optimization only,
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since a full 64-bit immediate OR can always be performed with 4 sequential
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OI[LH][LH] instructions. What we're looking for is immediates that we
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@ -571,25 +524,12 @@ static int tcg_target_const_match(tcg_target_long val,
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}
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/* Handle the modifiers. */
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if (ct & TCG_CT_CONST_NEG) {
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val = -val;
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}
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if (ct & TCG_CT_CONST_32) {
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val = (int32_t)val;
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}
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/* The following are mutually exclusive. */
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if (ct & TCG_CT_CONST_ADDI) {
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/* Immediates that may be used with add. If we have the
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extended-immediates facility then we have ADD IMMEDIATE
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with signed and unsigned 32-bit, otherwise we have only
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ADD HALFWORD IMMEDIATE with a signed 16-bit. */
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if (facilities & FACILITY_EXT_IMM) {
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return val == (int32_t)val || val == (uint32_t)val;
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} else {
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return val == (int16_t)val;
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}
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} else if (ct & TCG_CT_CONST_MULI) {
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if (ct & TCG_CT_CONST_MULI) {
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/* Immediates that may be used with multiply. If we have the
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general-instruction-extensions, then we have MULTIPLY SINGLE
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IMMEDIATE with a signed 32-bit, otherwise we have only
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@ -599,8 +539,6 @@ static int tcg_target_const_match(tcg_target_long val,
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} else {
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return val == (int16_t)val;
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}
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} else if (ct & TCG_CT_CONST_ANDI) {
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return tcg_match_andi(ct, val);
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} else if (ct & TCG_CT_CONST_ORI) {
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return tcg_match_ori(ct, val);
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} else if (ct & TCG_CT_CONST_XORI) {
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@ -625,6 +563,12 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
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tcg_out32(s, (op << 16) | (r1 << 4) | r2);
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}
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static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
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TCGReg r1, TCGReg r2, int m3)
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{
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tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
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}
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static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
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{
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tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
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@ -770,7 +714,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
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/* If we get here, both the high and low parts have non-zero bits. */
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/* Recurse to load the lower 32-bits. */
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tcg_out_movi(s, TCG_TYPE_I32, ret, sval);
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tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff);
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/* Insert data into the high 32-bits. */
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uval = uval >> 31 >> 1;
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@ -804,10 +748,11 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
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tcg_target_long ofs)
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{
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if (ofs < -0x80000 || ofs >= 0x80000) {
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/* Combine the low 16 bits of the offset with the actual load insn;
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the high 48 bits must come from an immediate load. */
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs & ~0xffff);
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ofs &= 0xffff;
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/* Combine the low 20 bits of the offset with the actual load insn;
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the high 44 bits must come from an immediate load. */
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tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
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ofs = low;
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/* If we were already given an index register, add it in. */
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if (index != TCG_REG_NONE) {
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@ -866,6 +811,15 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
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tcg_out_ld(s, type, dest, dest, addr & 0xffff);
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}
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static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
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int msb, int lsb, int ofs, int z)
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{
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/* Format RIE-f */
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tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
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tcg_out16(s, (msb << 8) | (z << 7) | lsb);
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tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
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}
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static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
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{
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if (facilities & FACILITY_EXT_IMM) {
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@ -956,30 +910,37 @@ static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
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tcg_out_insn(s, RRE, LLGFR, dest, src);
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}
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static inline void tgen32_addi(TCGContext *s, TCGReg dest, int32_t val)
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/* Accept bit patterns like these:
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0....01....1
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1....10....0
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1..10..01..1
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0..01..10..0
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Copied from gcc sources. */
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static inline bool risbg_mask(uint64_t c)
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{
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if (val == (int16_t)val) {
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tcg_out_insn(s, RI, AHI, dest, val);
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} else {
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tcg_out_insn(s, RIL, AFI, dest, val);
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uint64_t lsb;
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LSB zero. */
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if (c & 1) {
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c = ~c;
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}
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/* Reject all zeros or all ones. */
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if (c == 0) {
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return false;
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}
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/* Find the first transition. */
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lsb = c & -c;
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/* Invert to look for a second transition. */
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c = ~c;
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/* Erase the first transition. */
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c &= -lsb;
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/* Find the second transition, if any. */
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lsb = c & -c;
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/* Match if all the bits are 1's, or if c is zero. */
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return c == -lsb;
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}
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static inline void tgen64_addi(TCGContext *s, TCGReg dest, int64_t val)
|
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{
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if (val == (int16_t)val) {
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tcg_out_insn(s, RI, AGHI, dest, val);
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} else if (val == (int32_t)val) {
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tcg_out_insn(s, RIL, AGFI, dest, val);
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} else if (val == (uint32_t)val) {
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tcg_out_insn(s, RIL, ALGFI, dest, val);
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} else {
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tcg_abort();
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}
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}
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static void tgen64_andi(TCGContext *s, TCGReg dest, tcg_target_ulong val)
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static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
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{
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static const S390Opcode ni_insns[4] = {
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RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
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@ -987,63 +948,64 @@ static void tgen64_andi(TCGContext *s, TCGReg dest, tcg_target_ulong val)
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static const S390Opcode nif_insns[2] = {
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RIL_NILF, RIL_NIHF
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};
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uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
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int i;
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/* Look for no-op. */
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if (val == -1) {
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return;
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}
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/* Look for the zero-extensions. */
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if (val == 0xffffffff) {
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if ((val & valid) == 0xffffffff) {
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tgen_ext32u(s, dest, dest);
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return;
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}
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if (facilities & FACILITY_EXT_IMM) {
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if (val == 0xff) {
|
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if ((val & valid) == 0xff) {
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tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
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return;
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}
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if (val == 0xffff) {
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if ((val & valid) == 0xffff) {
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tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
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return;
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}
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}
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/* Try all 32-bit insns that can perform it in one go. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = ~(0xffffull << i*16);
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if ((val & mask) == mask) {
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tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
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/* Try all 32-bit insns that can perform it in one go. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = ~(0xffffull << i*16);
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if (((val | ~valid) & mask) == mask) {
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tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
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return;
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}
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}
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/* Try all 48-bit insns that can perform it in one go. */
|
||||
if (facilities & FACILITY_EXT_IMM) {
|
||||
for (i = 0; i < 2; i++) {
|
||||
tcg_target_ulong mask = ~(0xffffffffull << i*32);
|
||||
if (((val | ~valid) & mask) == mask) {
|
||||
tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Try all 48-bit insns that can perform it in one go. */
|
||||
if (facilities & FACILITY_EXT_IMM) {
|
||||
for (i = 0; i < 2; i++) {
|
||||
tcg_target_ulong mask = ~(0xffffffffull << i*32);
|
||||
if ((val & mask) == mask) {
|
||||
tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
|
||||
int msb, lsb;
|
||||
if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
|
||||
/* Achieve wraparound by swapping msb and lsb. */
|
||||
msb = 63 - ctz64(~val);
|
||||
lsb = clz64(~val) + 1;
|
||||
} else {
|
||||
msb = clz64(val);
|
||||
lsb = 63 - ctz64(val);
|
||||
}
|
||||
tcg_out_risbg(s, dest, dest, msb, lsb, 0, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Perform the AND via sequential modifications to the high and low
|
||||
parts. Do this via recursion to handle 16-bit vs 32-bit masks in
|
||||
each half. */
|
||||
tgen64_andi(s, dest, val | 0xffffffff00000000ull);
|
||||
tgen64_andi(s, dest, val | 0x00000000ffffffffull);
|
||||
/* Fall back to loading the constant. */
|
||||
tcg_out_movi(s, type, TCG_TMP0, val);
|
||||
if (type == TCG_TYPE_I32) {
|
||||
tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
|
||||
} else {
|
||||
/* With no extended-immediate facility, just emit the sequence. */
|
||||
for (i = 0; i < 4; i++) {
|
||||
tcg_target_ulong mask = 0xffffull << i*16;
|
||||
if ((val & mask) != mask) {
|
||||
tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
|
||||
}
|
||||
}
|
||||
tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1156,9 +1118,9 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
|
||||
}
|
||||
|
||||
static void tgen_setcond(TCGContext *s, TCGType type, TCGCond c,
|
||||
TCGReg dest, TCGReg r1, TCGArg c2, int c2const)
|
||||
TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
|
||||
{
|
||||
int cc = tgen_cmp(s, type, c, r1, c2, c2const);
|
||||
int cc = tgen_cmp(s, type, c, c1, c2, c2const);
|
||||
|
||||
/* Emit: r1 = 1; if (cc) goto over; r1 = 0; over: */
|
||||
tcg_out_movi(s, type, dest, 1);
|
||||
@ -1166,6 +1128,36 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond c,
|
||||
tcg_out_movi(s, type, dest, 0);
|
||||
}
|
||||
|
||||
static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
|
||||
TCGReg c1, TCGArg c2, int c2const, TCGReg r3)
|
||||
{
|
||||
int cc;
|
||||
if (facilities & FACILITY_LOAD_ON_COND) {
|
||||
cc = tgen_cmp(s, type, c, c1, c2, c2const);
|
||||
tcg_out_insn(s, RRF, LOCGR, dest, r3, cc);
|
||||
} else {
|
||||
c = tcg_invert_cond(c);
|
||||
cc = tgen_cmp(s, type, c, c1, c2, c2const);
|
||||
|
||||
/* Emit: if (cc) goto over; dest = r3; over: */
|
||||
tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
|
||||
tcg_out_insn(s, RRE, LGR, dest, r3);
|
||||
}
|
||||
}
|
||||
|
||||
bool tcg_target_deposit_valid(int ofs, int len)
|
||||
{
|
||||
return (facilities & FACILITY_GEN_INST_EXT) != 0;
|
||||
}
|
||||
|
||||
static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
|
||||
int ofs, int len)
|
||||
{
|
||||
int lsb = (63 - ofs);
|
||||
int msb = lsb - (len - 1);
|
||||
tcg_out_risbg(s, dest, src, msb, lsb, ofs, 0);
|
||||
}
|
||||
|
||||
static void tgen_gotoi(TCGContext *s, int cc, tcg_target_long dest)
|
||||
{
|
||||
tcg_target_long off = (dest - (tcg_target_long)s->code_ptr) >> 1;
|
||||
@ -1239,7 +1231,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
|
||||
int cc;
|
||||
|
||||
if (facilities & FACILITY_GEN_INST_EXT) {
|
||||
bool is_unsigned = (c > TCG_COND_GT);
|
||||
bool is_unsigned = is_unsigned_cond(c);
|
||||
bool in_range;
|
||||
S390Opcode opc;
|
||||
|
||||
@ -1405,37 +1397,29 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data,
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
static void tgen64_andi_tmp(TCGContext *s, TCGReg dest, tcg_target_ulong val)
|
||||
static TCGReg tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
||||
TCGReg addr_reg, int mem_index, int opc,
|
||||
uint16_t **label2_ptr_p, int is_store)
|
||||
{
|
||||
if (tcg_match_andi(0, val)) {
|
||||
tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, val);
|
||||
tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
|
||||
} else {
|
||||
tgen64_andi(s, dest, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
||||
TCGReg addr_reg, int mem_index, int opc,
|
||||
uint16_t **label2_ptr_p, int is_store)
|
||||
{
|
||||
const TCGReg arg0 = TCG_REG_R2;
|
||||
const TCGReg arg1 = TCG_REG_R3;
|
||||
const TCGReg arg0 = tcg_target_call_iarg_regs[0];
|
||||
const TCGReg arg1 = tcg_target_call_iarg_regs[1];
|
||||
const TCGReg arg2 = tcg_target_call_iarg_regs[2];
|
||||
const TCGReg arg3 = tcg_target_call_iarg_regs[3];
|
||||
int s_bits = opc & 3;
|
||||
uint16_t *label1_ptr;
|
||||
tcg_target_long ofs;
|
||||
|
||||
if (TARGET_LONG_BITS == 32) {
|
||||
tgen_ext32u(s, arg0, addr_reg);
|
||||
tgen_ext32u(s, arg1, addr_reg);
|
||||
} else {
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg1, addr_reg);
|
||||
}
|
||||
|
||||
tcg_out_sh64(s, RSY_SRLG, arg1, addr_reg, TCG_REG_NONE,
|
||||
tcg_out_sh64(s, RSY_SRLG, arg2, addr_reg, TCG_REG_NONE,
|
||||
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
|
||||
|
||||
tgen64_andi_tmp(s, arg0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
|
||||
tgen64_andi_tmp(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
||||
tgen_andi(s, TCG_TYPE_I64, arg1, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
|
||||
tgen_andi(s, TCG_TYPE_I64, arg2, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
||||
|
||||
if (is_store) {
|
||||
ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
|
||||
@ -1445,15 +1429,15 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
||||
assert(ofs < 0x80000);
|
||||
|
||||
if (TARGET_LONG_BITS == 32) {
|
||||
tcg_out_mem(s, RX_C, RXY_CY, arg0, arg1, TCG_AREG0, ofs);
|
||||
tcg_out_mem(s, RX_C, RXY_CY, arg1, arg2, TCG_AREG0, ofs);
|
||||
} else {
|
||||
tcg_out_mem(s, 0, RXY_CG, arg0, arg1, TCG_AREG0, ofs);
|
||||
tcg_out_mem(s, 0, RXY_CG, arg1, arg2, TCG_AREG0, ofs);
|
||||
}
|
||||
|
||||
if (TARGET_LONG_BITS == 32) {
|
||||
tgen_ext32u(s, arg0, addr_reg);
|
||||
tgen_ext32u(s, arg1, addr_reg);
|
||||
} else {
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg1, addr_reg);
|
||||
}
|
||||
|
||||
label1_ptr = (uint16_t*)s->code_ptr;
|
||||
@ -1467,56 +1451,42 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
||||
for the calling convention. */
|
||||
switch (opc) {
|
||||
case LD_UINT8:
|
||||
tgen_ext8u(s, TCG_TYPE_I64, arg1, data_reg);
|
||||
tgen_ext8u(s, TCG_TYPE_I64, arg2, data_reg);
|
||||
break;
|
||||
case LD_UINT16:
|
||||
tgen_ext16u(s, TCG_TYPE_I64, arg1, data_reg);
|
||||
tgen_ext16u(s, TCG_TYPE_I64, arg2, data_reg);
|
||||
break;
|
||||
case LD_UINT32:
|
||||
tgen_ext32u(s, arg1, data_reg);
|
||||
tgen_ext32u(s, arg2, data_reg);
|
||||
break;
|
||||
case LD_UINT64:
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg1, data_reg);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg2, data_reg);
|
||||
break;
|
||||
default:
|
||||
tcg_abort();
|
||||
}
|
||||
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
|
||||
/* XXX/FIXME: suboptimal */
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
|
||||
tcg_target_call_iarg_regs[2]);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
|
||||
tcg_target_call_iarg_regs[1]);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
|
||||
tcg_target_call_iarg_regs[0]);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
||||
TCG_AREG0);
|
||||
tcg_out_movi(s, TCG_TYPE_I32, arg3, mem_index);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg0, TCG_AREG0);
|
||||
tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
|
||||
} else {
|
||||
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
|
||||
/* XXX/FIXME: suboptimal */
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
|
||||
tcg_target_call_iarg_regs[1]);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
|
||||
tcg_target_call_iarg_regs[0]);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
||||
TCG_AREG0);
|
||||
tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, arg0, TCG_AREG0);
|
||||
tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
|
||||
|
||||
/* sign extension */
|
||||
switch (opc) {
|
||||
case LD_INT8:
|
||||
tgen_ext8s(s, TCG_TYPE_I64, data_reg, arg0);
|
||||
tgen_ext8s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
|
||||
break;
|
||||
case LD_INT16:
|
||||
tgen_ext16s(s, TCG_TYPE_I64, data_reg, arg0);
|
||||
tgen_ext16s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
|
||||
break;
|
||||
case LD_INT32:
|
||||
tgen_ext32s(s, data_reg, arg0);
|
||||
tgen_ext32s(s, data_reg, TCG_REG_R2);
|
||||
break;
|
||||
default:
|
||||
/* unsigned -> just copy */
|
||||
tcg_out_mov(s, TCG_TYPE_I64, data_reg, arg0);
|
||||
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1533,7 +1503,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
||||
ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
|
||||
assert(ofs < 0x80000);
|
||||
|
||||
tcg_out_mem(s, 0, RXY_AG, arg0, arg1, TCG_AREG0, ofs);
|
||||
tcg_out_mem(s, 0, RXY_AG, arg1, arg2, TCG_AREG0, ofs);
|
||||
|
||||
return arg1;
|
||||
}
|
||||
|
||||
static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr)
|
||||
@ -1579,10 +1551,10 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
mem_index = *args;
|
||||
|
||||
tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
|
||||
opc, &label2_ptr, 0);
|
||||
addr_reg = tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
|
||||
opc, &label2_ptr, 0);
|
||||
|
||||
tcg_out_qemu_ld_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
|
||||
tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, TCG_REG_NONE, 0);
|
||||
|
||||
tcg_finish_qemu_ldst(s, label2_ptr);
|
||||
#else
|
||||
@ -1608,10 +1580,10 @@ static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc)
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
mem_index = *args;
|
||||
|
||||
tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
|
||||
opc, &label2_ptr, 1);
|
||||
addr_reg = tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
|
||||
opc, &label2_ptr, 1);
|
||||
|
||||
tcg_out_qemu_st_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
|
||||
tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, TCG_REG_NONE, 0);
|
||||
|
||||
tcg_finish_qemu_ldst(s, label2_ptr);
|
||||
#else
|
||||
@ -1620,19 +1592,15 @@ static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if TCG_TARGET_REG_BITS == 64
|
||||
# define OP_32_64(x) \
|
||||
case glue(glue(INDEX_op_,x),_i32): \
|
||||
case glue(glue(INDEX_op_,x),_i64)
|
||||
#else
|
||||
# define OP_32_64(x) \
|
||||
case glue(glue(INDEX_op_,x),_i32)
|
||||
#endif
|
||||
|
||||
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
const TCGArg *args, const int *const_args)
|
||||
{
|
||||
S390Opcode op;
|
||||
TCGArg a0, a1, a2;
|
||||
|
||||
switch (opc) {
|
||||
case INDEX_op_exit_tb:
|
||||
@ -1708,23 +1676,38 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
break;
|
||||
|
||||
case INDEX_op_add_i32:
|
||||
a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
|
||||
if (const_args[2]) {
|
||||
tgen32_addi(s, args[0], args[2]);
|
||||
do_addi_32:
|
||||
if (a0 == a1) {
|
||||
if (a2 == (int16_t)a2) {
|
||||
tcg_out_insn(s, RI, AHI, a0, a2);
|
||||
break;
|
||||
}
|
||||
if (facilities & FACILITY_EXT_IMM) {
|
||||
tcg_out_insn(s, RIL, AFI, a0, a2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
|
||||
} else if (a0 == a1) {
|
||||
tcg_out_insn(s, RR, AR, a0, a2);
|
||||
} else {
|
||||
tcg_out_insn(s, RR, AR, args[0], args[2]);
|
||||
tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
|
||||
}
|
||||
break;
|
||||
case INDEX_op_sub_i32:
|
||||
a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
|
||||
if (const_args[2]) {
|
||||
tgen32_addi(s, args[0], -args[2]);
|
||||
} else {
|
||||
tcg_out_insn(s, RR, SR, args[0], args[2]);
|
||||
a2 = -a2;
|
||||
goto do_addi_32;
|
||||
}
|
||||
tcg_out_insn(s, RR, SR, args[0], args[2]);
|
||||
break;
|
||||
|
||||
case INDEX_op_and_i32:
|
||||
if (const_args[2]) {
|
||||
tgen64_andi(s, args[0], args[2] | 0xffffffff00000000ull);
|
||||
tgen_andi(s, TCG_TYPE_I32, args[0], args[2]);
|
||||
} else {
|
||||
tcg_out_insn(s, RR, NR, args[0], args[2]);
|
||||
}
|
||||
@ -1824,6 +1807,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
|
||||
break;
|
||||
|
||||
case INDEX_op_add2_i32:
|
||||
/* ??? Make use of ALFI. */
|
||||
tcg_out_insn(s, RR, ALR, args[0], args[4]);
|
||||
tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
|
||||
break;
|
||||
case INDEX_op_sub2_i32:
|
||||
/* ??? Make use of SLFI. */
|
||||
tcg_out_insn(s, RR, SLR, args[0], args[4]);
|
||||
tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
|
||||
break;
|
||||
|
||||
case INDEX_op_br:
|
||||
tgen_branch(s, S390_CC_ALWAYS, args[0]);
|
||||
break;
|
||||
@ -1836,6 +1830,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
|
||||
args[2], const_args[2]);
|
||||
break;
|
||||
case INDEX_op_movcond_i32:
|
||||
tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
|
||||
args[2], const_args[2], args[3]);
|
||||
break;
|
||||
|
||||
case INDEX_op_qemu_ld8u:
|
||||
tcg_out_qemu_ld(s, args, LD_UINT8);
|
||||
@ -1870,7 +1868,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
tcg_out_qemu_st(s, args, LD_UINT64);
|
||||
break;
|
||||
|
||||
#if TCG_TARGET_REG_BITS == 64
|
||||
case INDEX_op_mov_i64:
|
||||
tcg_out_mov(s, TCG_TYPE_I64, args[0], args[1]);
|
||||
break;
|
||||
@ -1899,15 +1896,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
break;
|
||||
|
||||
case INDEX_op_add_i64:
|
||||
a0 = args[0], a1 = args[1], a2 = args[2];
|
||||
if (const_args[2]) {
|
||||
tgen64_addi(s, args[0], args[2]);
|
||||
do_addi_64:
|
||||
if (a0 == a1) {
|
||||
if (a2 == (int16_t)a2) {
|
||||
tcg_out_insn(s, RI, AGHI, a0, a2);
|
||||
break;
|
||||
}
|
||||
if (facilities & FACILITY_EXT_IMM) {
|
||||
if (a2 == (int32_t)a2) {
|
||||
tcg_out_insn(s, RIL, AGFI, a0, a2);
|
||||
break;
|
||||
} else if (a2 == (uint32_t)a2) {
|
||||
tcg_out_insn(s, RIL, ALGFI, a0, a2);
|
||||
break;
|
||||
} else if (-a2 == (uint32_t)-a2) {
|
||||
tcg_out_insn(s, RIL, SLGFI, a0, -a2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
|
||||
} else if (a0 == a1) {
|
||||
tcg_out_insn(s, RRE, AGR, a0, a2);
|
||||
} else {
|
||||
tcg_out_insn(s, RRE, AGR, args[0], args[2]);
|
||||
tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
|
||||
}
|
||||
break;
|
||||
case INDEX_op_sub_i64:
|
||||
a0 = args[0], a1 = args[1], a2 = args[2];
|
||||
if (const_args[2]) {
|
||||
tgen64_addi(s, args[0], -args[2]);
|
||||
a2 = -a2;
|
||||
goto do_addi_64;
|
||||
} else {
|
||||
tcg_out_insn(s, RRE, SGR, args[0], args[2]);
|
||||
}
|
||||
@ -1915,7 +1936,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
|
||||
case INDEX_op_and_i64:
|
||||
if (const_args[2]) {
|
||||
tgen64_andi(s, args[0], args[2]);
|
||||
tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
|
||||
} else {
|
||||
tcg_out_insn(s, RRE, NGR, args[0], args[2]);
|
||||
}
|
||||
@ -1964,6 +1985,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
case INDEX_op_divu2_i64:
|
||||
tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
|
||||
break;
|
||||
case INDEX_op_mulu2_i64:
|
||||
tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
|
||||
break;
|
||||
|
||||
case INDEX_op_shl_i64:
|
||||
op = RSY_SLLG;
|
||||
@ -2020,6 +2044,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
tgen_ext32u(s, args[0], args[1]);
|
||||
break;
|
||||
|
||||
case INDEX_op_add2_i64:
|
||||
/* ??? Make use of ALGFI and SLGFI. */
|
||||
tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
|
||||
tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
|
||||
break;
|
||||
case INDEX_op_sub2_i64:
|
||||
/* ??? Make use of ALGFI and SLGFI. */
|
||||
tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
|
||||
tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
|
||||
break;
|
||||
|
||||
case INDEX_op_brcond_i64:
|
||||
tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
|
||||
args[1], const_args[1], args[3]);
|
||||
@ -2028,6 +2063,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
|
||||
args[2], const_args[2]);
|
||||
break;
|
||||
case INDEX_op_movcond_i64:
|
||||
tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
|
||||
args[2], const_args[2], args[3]);
|
||||
break;
|
||||
|
||||
case INDEX_op_qemu_ld32u:
|
||||
tcg_out_qemu_ld(s, args, LD_UINT32);
|
||||
@ -2035,7 +2074,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
case INDEX_op_qemu_ld32s:
|
||||
tcg_out_qemu_ld(s, args, LD_INT32);
|
||||
break;
|
||||
#endif /* TCG_TARGET_REG_BITS == 64 */
|
||||
|
||||
OP_32_64(deposit):
|
||||
tgen_deposit(s, args[0], args[2], args[3], args[4]);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr,"unimplemented opc 0x%x\n",opc);
|
||||
@ -2061,14 +2103,14 @@ static const TCGTargetOpDef s390_op_defs[] = {
|
||||
{ INDEX_op_st16_i32, { "r", "r" } },
|
||||
{ INDEX_op_st_i32, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add_i32, { "r", "0", "rWI" } },
|
||||
{ INDEX_op_sub_i32, { "r", "0", "rWNI" } },
|
||||
{ INDEX_op_add_i32, { "r", "r", "ri" } },
|
||||
{ INDEX_op_sub_i32, { "r", "0", "ri" } },
|
||||
{ INDEX_op_mul_i32, { "r", "0", "rK" } },
|
||||
|
||||
{ INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
|
||||
{ INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
|
||||
|
||||
{ INDEX_op_and_i32, { "r", "0", "rWA" } },
|
||||
{ INDEX_op_and_i32, { "r", "0", "ri" } },
|
||||
{ INDEX_op_or_i32, { "r", "0", "rWO" } },
|
||||
{ INDEX_op_xor_i32, { "r", "0", "rWX" } },
|
||||
|
||||
@ -2089,8 +2131,13 @@ static const TCGTargetOpDef s390_op_defs[] = {
|
||||
{ INDEX_op_bswap16_i32, { "r", "r" } },
|
||||
{ INDEX_op_bswap32_i32, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "r", "r" } },
|
||||
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "r", "r" } },
|
||||
|
||||
{ INDEX_op_brcond_i32, { "r", "rWC" } },
|
||||
{ INDEX_op_setcond_i32, { "r", "r", "rWC" } },
|
||||
{ INDEX_op_movcond_i32, { "r", "r", "rWC", "r", "0" } },
|
||||
{ INDEX_op_deposit_i32, { "r", "0", "r" } },
|
||||
|
||||
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
||||
@ -2104,7 +2151,6 @@ static const TCGTargetOpDef s390_op_defs[] = {
|
||||
{ INDEX_op_qemu_st32, { "L", "L" } },
|
||||
{ INDEX_op_qemu_st64, { "L", "L" } },
|
||||
|
||||
#if defined(__s390x__)
|
||||
{ INDEX_op_mov_i64, { "r", "r" } },
|
||||
{ INDEX_op_movi_i64, { "r" } },
|
||||
|
||||
@ -2121,14 +2167,15 @@ static const TCGTargetOpDef s390_op_defs[] = {
|
||||
{ INDEX_op_st32_i64, { "r", "r" } },
|
||||
{ INDEX_op_st_i64, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add_i64, { "r", "0", "rI" } },
|
||||
{ INDEX_op_sub_i64, { "r", "0", "rNI" } },
|
||||
{ INDEX_op_add_i64, { "r", "r", "ri" } },
|
||||
{ INDEX_op_sub_i64, { "r", "0", "ri" } },
|
||||
{ INDEX_op_mul_i64, { "r", "0", "rK" } },
|
||||
|
||||
{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
|
||||
{ INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
|
||||
{ INDEX_op_mulu2_i64, { "b", "a", "0", "r" } },
|
||||
|
||||
{ INDEX_op_and_i64, { "r", "0", "rA" } },
|
||||
{ INDEX_op_and_i64, { "r", "0", "ri" } },
|
||||
{ INDEX_op_or_i64, { "r", "0", "rO" } },
|
||||
{ INDEX_op_xor_i64, { "r", "0", "rX" } },
|
||||
|
||||
@ -2152,12 +2199,16 @@ static const TCGTargetOpDef s390_op_defs[] = {
|
||||
{ INDEX_op_bswap32_i64, { "r", "r" } },
|
||||
{ INDEX_op_bswap64_i64, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add2_i64, { "r", "r", "0", "1", "r", "r" } },
|
||||
{ INDEX_op_sub2_i64, { "r", "r", "0", "1", "r", "r" } },
|
||||
|
||||
{ INDEX_op_brcond_i64, { "r", "rC" } },
|
||||
{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
|
||||
{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
|
||||
{ INDEX_op_deposit_i64, { "r", "0", "r" } },
|
||||
|
||||
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
||||
#endif
|
||||
|
||||
{ -1 },
|
||||
};
|
||||
@ -2302,17 +2353,24 @@ static void tcg_target_init(TCGContext *s)
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
|
||||
|
||||
tcg_add_target_add_op_defs(s390_op_defs);
|
||||
tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
|
||||
CPU_TEMP_BUF_NLONGS * sizeof(long));
|
||||
}
|
||||
|
||||
static void tcg_target_qemu_prologue(TCGContext *s)
|
||||
{
|
||||
tcg_target_long frame_size;
|
||||
|
||||
/* stmg %r6,%r15,48(%r15) (save registers) */
|
||||
tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
|
||||
|
||||
/* aghi %r15,-160 (stack frame) */
|
||||
tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -160);
|
||||
/* aghi %r15,-frame_size */
|
||||
frame_size = TCG_TARGET_CALL_STACK_OFFSET;
|
||||
frame_size += TCG_STATIC_CALL_ARGS_SIZE;
|
||||
frame_size += CPU_TEMP_BUF_NLONGS * sizeof(long);
|
||||
tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -frame_size);
|
||||
|
||||
tcg_set_frame(s, TCG_REG_CALL_STACK,
|
||||
TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
|
||||
CPU_TEMP_BUF_NLONGS * sizeof(long));
|
||||
|
||||
if (GUEST_BASE >= 0x80000) {
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
|
||||
@ -2325,8 +2383,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
|
||||
|
||||
tb_ret_addr = s->code_ptr;
|
||||
|
||||
/* lmg %r6,%r15,208(%r15) (restore registers) */
|
||||
tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 208);
|
||||
/* lmg %r6,%r15,fs+48(%r15) (restore registers) */
|
||||
tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
|
||||
frame_size + 48);
|
||||
|
||||
/* br %r14 (return) */
|
||||
tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
|
||||
|
||||
@ -63,14 +63,13 @@ typedef enum TCGReg {
|
||||
#define TCG_TARGET_HAS_eqv_i32 0
|
||||
#define TCG_TARGET_HAS_nand_i32 0
|
||||
#define TCG_TARGET_HAS_nor_i32 0
|
||||
#define TCG_TARGET_HAS_deposit_i32 0
|
||||
#define TCG_TARGET_HAS_movcond_i32 0
|
||||
#define TCG_TARGET_HAS_add2_i32 0
|
||||
#define TCG_TARGET_HAS_sub2_i32 0
|
||||
#define TCG_TARGET_HAS_deposit_i32 1
|
||||
#define TCG_TARGET_HAS_movcond_i32 1
|
||||
#define TCG_TARGET_HAS_add2_i32 1
|
||||
#define TCG_TARGET_HAS_sub2_i32 1
|
||||
#define TCG_TARGET_HAS_mulu2_i32 0
|
||||
#define TCG_TARGET_HAS_muls2_i32 0
|
||||
|
||||
#if TCG_TARGET_REG_BITS == 64
|
||||
#define TCG_TARGET_HAS_div2_i64 1
|
||||
#define TCG_TARGET_HAS_rot_i64 1
|
||||
#define TCG_TARGET_HAS_ext8s_i64 1
|
||||
@ -89,18 +88,21 @@ typedef enum TCGReg {
|
||||
#define TCG_TARGET_HAS_eqv_i64 0
|
||||
#define TCG_TARGET_HAS_nand_i64 0
|
||||
#define TCG_TARGET_HAS_nor_i64 0
|
||||
#define TCG_TARGET_HAS_deposit_i64 0
|
||||
#define TCG_TARGET_HAS_movcond_i64 0
|
||||
#define TCG_TARGET_HAS_add2_i64 0
|
||||
#define TCG_TARGET_HAS_sub2_i64 0
|
||||
#define TCG_TARGET_HAS_mulu2_i64 0
|
||||
#define TCG_TARGET_HAS_deposit_i64 1
|
||||
#define TCG_TARGET_HAS_movcond_i64 1
|
||||
#define TCG_TARGET_HAS_add2_i64 1
|
||||
#define TCG_TARGET_HAS_sub2_i64 1
|
||||
#define TCG_TARGET_HAS_mulu2_i64 1
|
||||
#define TCG_TARGET_HAS_muls2_i64 0
|
||||
#endif
|
||||
|
||||
extern bool tcg_target_deposit_valid(int ofs, int len);
|
||||
#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid
|
||||
#define TCG_TARGET_deposit_i64_valid tcg_target_deposit_valid
|
||||
|
||||
/* used for function call generation */
|
||||
#define TCG_REG_CALL_STACK TCG_REG_R15
|
||||
#define TCG_TARGET_STACK_ALIGN 8
|
||||
#define TCG_TARGET_CALL_STACK_OFFSET 0
|
||||
#define TCG_TARGET_CALL_STACK_OFFSET 160
|
||||
|
||||
#define TCG_TARGET_EXTEND_ARGS 1
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user