mmu-hash32: Split out handling of direct store segments
At present a large chunk of ppc_hash32_translate() is taken up with an ugly if selecting between direct store segments (hardly ever used) and normal paged segments. This patch clarifies the flow of code by handling direct store segments immediately then returning, leaving the straight line code to describe the normal MMU path. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
65d61643d0
commit
4b9605a5b1
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@ -381,7 +381,7 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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{
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hwaddr hash;
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target_ulong vsid;
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int ds, pr, target_page_bits;
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int pr, target_page_bits;
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int ret, ret2;
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target_ulong sr, pgidx;
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@ -401,91 +401,21 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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}
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}
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pr = msr_pr;
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/* 3. Look up the Segment Register */
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sr = env->sr[eaddr >> 28];
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pr = msr_pr;
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ctx->key = (((sr & SR32_KP) && (pr != 0)) ||
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((sr & SR32_KS) && (pr == 0))) ? 1 : 0;
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ds = !!(sr & SR32_T);
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ctx->nx = !!(sr & SR32_NX);
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vsid = sr & SR32_VSID;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, rwx);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, ds, ctx->nx, vsid);
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ret = -1;
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if (!ds) {
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/* Check if instruction fetch is allowed, if needed */
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if (rwx != 2 || ctx->nx == 0) {
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (hwaddr)-1ULL;
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ctx->ptem,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte32(env, ctx, eaddr, 0, rwx, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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ret2 = find_pte32(env, ctx, eaddr, 1, rwx, target_page_bits);
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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hwaddr curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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"\n", sdr, mask + 0x80);
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for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
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curaddr += 16) {
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a0 = ldl_phys(curaddr);
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a1 = ldl_phys(curaddr + 4);
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a2 = ldl_phys(curaddr + 8);
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a3 = ldl_phys(curaddr + 12);
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if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
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qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
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curaddr, a0, a1, a2, a3);
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}
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}
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}
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#endif
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} else {
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LOG_MMU("No access allowed\n");
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ret = -3;
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}
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} else {
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target_ulong sr;
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/* 4. Handle direct store segments */
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if (sr & SR32_T) {
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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@ -528,12 +458,82 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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}
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if ((rwx == 1 || ctx->key != 1) && (rwx == 0 || ctx->key != 0)) {
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ctx->raddr = eaddr;
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ret = 2;
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return 2;
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} else {
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ret = -2;
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return -2;
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}
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}
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ctx->nx = !!(sr & SR32_NX);
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vsid = sr & SR32_VSID;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, rwx);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, ctx->nx, vsid);
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ret = -1;
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/* Check if instruction fetch is allowed, if needed */
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if (rwx != 2 || ctx->nx == 0) {
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (hwaddr)-1ULL;
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ctx->ptem,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte32(env, ctx, eaddr, 0, rwx, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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ret2 = find_pte32(env, ctx, eaddr, 1, rwx, target_page_bits);
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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hwaddr curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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"\n", sdr, mask + 0x80);
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for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
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curaddr += 16) {
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a0 = ldl_phys(curaddr);
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a1 = ldl_phys(curaddr + 4);
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a2 = ldl_phys(curaddr + 8);
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a3 = ldl_phys(curaddr + 12);
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if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
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qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
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curaddr, a0, a1, a2, a3);
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}
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}
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}
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#endif
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} else {
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LOG_MMU("No access allowed\n");
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ret = -3;
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}
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return ret;
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}
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