Fix usp/isp swapping upon clrpsw/setpsw.
Fix psw.i/pc upon wait. Align dtb in ram. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJhlJYdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ipQf+JLeXW1HaD5iNnyUl Uh0CLvwwkXvuiDAlaoGCKl2mcVJR/2d/ScTPTGx44VEwmLpV2mgF8/VUWoRtao/C Kal5DsaOAC2pUKkYbnorsCpq4ty2QMPYXZXOKULPcfLa3tbsr9bE6JkCQ6gZeAAk ITuB+dfdBTpW2lc0eoQ7cDMcQkD1cxyfNVwZ7rP2i9N6tjTW1488kxsBthhQIr0t sNrrBIiK7nhdgXNfhWDPP/6f8osZwhLGO8G9tyOTtkPOF6o6Dy27B0Bmlf5T6OY+ SeTwC2O197gd0YkPWvZgMQbJWnX0kHgHwlFEBaMSxMXAcrlccNZQMyBN4cYoC+ie e3vyWA== =lj1s -----END PGP SIGNATURE----- Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into staging Fix usp/isp swapping upon clrpsw/setpsw. Fix psw.i/pc upon wait. Align dtb in ram. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJhlJYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ipQf+JLeXW1HaD5iNnyUl # Uh0CLvwwkXvuiDAlaoGCKl2mcVJR/2d/ScTPTGx44VEwmLpV2mgF8/VUWoRtao/C # Kal5DsaOAC2pUKkYbnorsCpq4ty2QMPYXZXOKULPcfLa3tbsr9bE6JkCQ6gZeAAk # ITuB+dfdBTpW2lc0eoQ7cDMcQkD1cxyfNVwZ7rP2i9N6tjTW1488kxsBthhQIr0t # sNrrBIiK7nhdgXNfhWDPP/6f8osZwhLGO8G9tyOTtkPOF6o6Dy27B0Bmlf5T6OY+ # SeTwC2O197gd0YkPWvZgMQbJWnX0kHgHwlFEBaMSxMXAcrlccNZQMyBN4cYoC+ie # e3vyWA== # =lj1s # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 Apr 2022 10:29:58 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu: target/rx: update PC correctly in wait instruction target/rx: set PSW.I when executing wait instruction hw/rx: rx-gdbsim DTB load address aligned of 16byte. target/rx: Swap stack pointers on clrpsw/setpsw instruction target/rx: Move DISAS_UPDATE check for write to PSW target/rx: Store PSW.U in tb->flags target/rx: Put tb_flags into DisasContext Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
4ba2565831
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@ -141,7 +141,7 @@ static void rx_gdbsim_init(MachineState *machine)
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exit(1);
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}
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/* DTB is located at the end of SDRAM space. */
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dtb_offset = machine->ram_size - dtb_size;
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dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16);
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rom_add_blob_fixed("dtb", dtb, dtb_size,
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SDRAM_BASE + dtb_offset);
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/* Set dtb address to R1 */
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@ -149,6 +149,7 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
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*pc = env->pc;
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*cs_base = 0;
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*flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
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*flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
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}
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static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
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@ -450,6 +450,7 @@ G_NORETURN void helper_wait(CPURXState *env)
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cs->halted = 1;
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env->in_sleep = 1;
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env->psw_i = 1;
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raise_exception(env, EXCP_HLT, 0);
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}
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@ -32,6 +32,7 @@ typedef struct DisasContext {
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DisasContextBase base;
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CPURXState *env;
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uint32_t pc;
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uint32_t tb_flags;
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} DisasContext;
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typedef struct DisasCompare {
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@ -231,7 +232,7 @@ static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem,
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/* Processor mode check */
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static int is_privileged(DisasContext *ctx, int is_exception)
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{
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if (FIELD_EX32(ctx->base.tb->flags, PSW, PM)) {
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if (FIELD_EX32(ctx->tb_flags, PSW, PM)) {
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if (is_exception) {
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gen_helper_raise_privilege_violation(cpu_env);
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}
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@ -310,9 +311,8 @@ static void psw_cond(DisasCompare *dc, uint32_t cond)
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}
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}
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static void move_from_cr(TCGv ret, int cr, uint32_t pc)
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static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc)
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{
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TCGv z = tcg_const_i32(0);
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switch (cr) {
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case 0: /* PSW */
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gen_helper_pack_psw(ret, cpu_env);
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@ -321,8 +321,11 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc)
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tcg_gen_movi_i32(ret, pc);
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break;
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case 2: /* USP */
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tcg_gen_movcond_i32(TCG_COND_NE, ret,
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cpu_psw_u, z, cpu_sp, cpu_usp);
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if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
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tcg_gen_mov_i32(ret, cpu_sp);
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} else {
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tcg_gen_mov_i32(ret, cpu_usp);
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}
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break;
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case 3: /* FPSW */
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tcg_gen_mov_i32(ret, cpu_fpsw);
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@ -334,8 +337,11 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc)
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tcg_gen_mov_i32(ret, cpu_bpc);
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break;
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case 10: /* ISP */
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tcg_gen_movcond_i32(TCG_COND_EQ, ret,
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cpu_psw_u, z, cpu_sp, cpu_isp);
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if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
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tcg_gen_mov_i32(ret, cpu_isp);
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} else {
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tcg_gen_mov_i32(ret, cpu_sp);
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}
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break;
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case 11: /* FINTV */
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tcg_gen_mov_i32(ret, cpu_fintv);
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@ -349,28 +355,31 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc)
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tcg_gen_movi_i32(ret, 0);
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break;
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}
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tcg_temp_free(z);
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}
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static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
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{
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TCGv z;
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if (cr >= 8 && !is_privileged(ctx, 0)) {
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/* Some control registers can only be written in privileged mode. */
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qemu_log_mask(LOG_GUEST_ERROR,
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"disallow control register write %s", rx_crname(cr));
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return;
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}
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z = tcg_const_i32(0);
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switch (cr) {
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case 0: /* PSW */
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gen_helper_set_psw(cpu_env, val);
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if (is_privileged(ctx, 0)) {
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/* PSW.{I,U} may be updated here. exit TB. */
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ctx->base.is_jmp = DISAS_UPDATE;
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}
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break;
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/* case 1: to PC not supported */
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case 2: /* USP */
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tcg_gen_mov_i32(cpu_usp, val);
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tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp,
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cpu_psw_u, z, cpu_usp, cpu_sp);
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if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
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tcg_gen_mov_i32(cpu_sp, val);
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} else {
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tcg_gen_mov_i32(cpu_usp, val);
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}
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break;
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case 3: /* FPSW */
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gen_helper_set_fpsw(cpu_env, val);
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@ -382,10 +391,11 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
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tcg_gen_mov_i32(cpu_bpc, val);
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break;
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case 10: /* ISP */
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tcg_gen_mov_i32(cpu_isp, val);
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/* if PSW.U is 0, copy isp to r0 */
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tcg_gen_movcond_i32(TCG_COND_EQ, cpu_sp,
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cpu_psw_u, z, cpu_isp, cpu_sp);
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if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
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tcg_gen_mov_i32(cpu_isp, val);
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} else {
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tcg_gen_mov_i32(cpu_sp, val);
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}
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break;
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case 11: /* FINTV */
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tcg_gen_mov_i32(cpu_fintv, val);
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@ -398,7 +408,6 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
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"Unimplement control register %d", cr);
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break;
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}
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tcg_temp_free(z);
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}
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static void push(TCGv val)
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@ -626,10 +635,6 @@ static bool trans_POPC(DisasContext *ctx, arg_POPC *a)
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val = tcg_temp_new();
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pop(val);
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move_to_cr(ctx, val, a->cr);
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if (a->cr == 0 && is_privileged(ctx, 0)) {
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/* PSW.I may be updated here. exit TB. */
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ctx->base.is_jmp = DISAS_UPDATE;
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}
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tcg_temp_free(val);
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return true;
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}
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@ -682,7 +687,7 @@ static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a)
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{
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TCGv val;
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val = tcg_temp_new();
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move_from_cr(val, a->cr, ctx->pc);
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move_from_cr(ctx, val, a->cr, ctx->pc);
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push(val);
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tcg_temp_free(val);
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return true;
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@ -2160,7 +2165,12 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
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ctx->base.is_jmp = DISAS_UPDATE;
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break;
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case PSW_U:
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tcg_gen_movi_i32(cpu_psw_u, val);
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if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) {
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ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val);
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tcg_gen_movi_i32(cpu_psw_u, val);
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tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp);
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tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
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@ -2200,9 +2210,6 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
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imm = tcg_const_i32(a->imm);
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move_to_cr(ctx, imm, a->cr);
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if (a->cr == 0 && is_privileged(ctx, 0)) {
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ctx->base.is_jmp = DISAS_UPDATE;
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}
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tcg_temp_free(imm);
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return true;
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}
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@ -2211,16 +2218,13 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
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static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a)
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{
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move_to_cr(ctx, cpu_regs[a->rs], a->cr);
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if (a->cr == 0 && is_privileged(ctx, 0)) {
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ctx->base.is_jmp = DISAS_UPDATE;
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}
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return true;
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}
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/* mvfc rs, rd */
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static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a)
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{
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move_from_cr(cpu_regs[a->rd], a->cr, ctx->pc);
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move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc);
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return true;
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}
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@ -2281,7 +2285,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
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static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
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{
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if (is_privileged(ctx, 1)) {
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tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
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tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
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gen_helper_wait(cpu_env);
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}
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return true;
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@ -2292,6 +2296,7 @@ static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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CPURXState *env = cs->env_ptr;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx->env = env;
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ctx->tb_flags = ctx->base.tb->flags;
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}
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static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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