target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro

Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240129164514.73104-19-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2024-01-29 17:45:00 +01:00 committed by Thomas Huth
parent da9536433f
commit 4c44a98051
9 changed files with 24 additions and 50 deletions

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@ -80,8 +80,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int i; int i;
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
@ -123,9 +122,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address)
static void mips_cpu_set_pc(CPUState *cs, vaddr value) static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); mips_env_set_pc(cpu_env(cs), value);
mips_env_set_pc(&cpu->env, value);
} }
static vaddr mips_cpu_get_pc(CPUState *cs) static vaddr mips_cpu_get_pc(CPUState *cs)
@ -137,8 +134,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs)
static bool mips_cpu_has_work(CPUState *cs) static bool mips_cpu_has_work(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
bool has_work = false; bool has_work = false;
/* /*
@ -433,10 +429,7 @@ static void mips_cpu_reset_hold(Object *obj)
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{ {
MIPSCPU *cpu = MIPS_CPU(s); if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
CPUMIPSState *env = &cpu->env;
if (!(env->insn_flags & ISA_NANOMIPS32)) {
#if TARGET_BIG_ENDIAN #if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips; info->print_insn = print_insn_big_mips;
#else #else

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@ -25,8 +25,7 @@
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
if (n < 32) { if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
@ -78,8 +77,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
target_ulong tmp; target_ulong tmp;
tmp = ldtul_p(mem_buf); tmp = ldtul_p(mem_buf);

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@ -63,8 +63,7 @@ int kvm_arch_irqchip_create(KVMState *s)
int kvm_arch_init_vcpu(CPUState *cs) int kvm_arch_init_vcpu(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int ret = 0; int ret = 0;
qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
@ -460,8 +459,7 @@ static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,
*/ */
static int kvm_mips_save_count(CPUState *cs) static int kvm_mips_save_count(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
uint64_t count_ctl; uint64_t count_ctl;
int err, ret = 0; int err, ret = 0;
@ -502,8 +500,7 @@ static int kvm_mips_save_count(CPUState *cs)
*/ */
static int kvm_mips_restore_count(CPUState *cs) static int kvm_mips_restore_count(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
uint64_t count_ctl; uint64_t count_ctl;
int err_dc, err, ret = 0; int err_dc, err, ret = 0;
@ -590,8 +587,7 @@ static void kvm_mips_update_state(void *opaque, bool running, RunState state)
static int kvm_mips_put_fpu_registers(CPUState *cs, int level) static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int err, ret = 0; int err, ret = 0;
unsigned int i; unsigned int i;
@ -670,8 +666,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
static int kvm_mips_get_fpu_registers(CPUState *cs) static int kvm_mips_get_fpu_registers(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int err, ret = 0; int err, ret = 0;
unsigned int i; unsigned int i;
@ -751,8 +746,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
static int kvm_mips_put_cp0_registers(CPUState *cs, int level) static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int err, ret = 0; int err, ret = 0;
(void)level; (void)level;
@ -974,8 +968,7 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
static int kvm_mips_get_cp0_registers(CPUState *cs) static int kvm_mips_get_cp0_registers(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int err, ret = 0; int err, ret = 0;
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
@ -1181,8 +1174,7 @@ static int kvm_mips_get_cp0_registers(CPUState *cs)
int kvm_arch_put_registers(CPUState *cs, int level) int kvm_arch_put_registers(CPUState *cs, int level)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
struct kvm_regs regs; struct kvm_regs regs;
int ret; int ret;
int i; int i;
@ -1217,8 +1209,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
int kvm_arch_get_registers(CPUState *cs) int kvm_arch_get_registers(CPUState *cs)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int ret = 0; int ret = 0;
struct kvm_regs regs; struct kvm_regs regs;
int i; int i;

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@ -230,8 +230,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
hwaddr phys_addr; hwaddr phys_addr;
int prot; int prot;

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@ -79,8 +79,7 @@ void helper_wait(CPUMIPSState *env)
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->active_tc.PC = tb->pc; env->active_tc.PC = tb->pc;

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@ -279,8 +279,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr) int mmu_idx, uintptr_t retaddr)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
int error_code = 0; int error_code = 0;
int excp; int excp;
@ -306,9 +305,8 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
int mmu_idx, MemTxAttrs attrs, int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr) MemTxResult response, uintptr_t retaddr)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cs);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
if (access_type == MMU_INST_FETCH) { if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr); do_raise_exception(env, EXCP_IBE, retaddr);

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@ -90,8 +90,7 @@ static void debug_post_eret(CPUMIPSState *env)
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) { && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {

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@ -906,8 +906,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx, MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr) bool probe, uintptr_t retaddr)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
hwaddr physical; hwaddr physical;
int prot; int prot;
int ret = TLBRET_BADADDR; int ret = TLBRET_BADADDR;
@ -1340,8 +1339,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{ {
if (interrupt_request & CPU_INTERRUPT_HARD) { if (interrupt_request & CPU_INTERRUPT_HARD) {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
if (cpu_mips_hw_interrupts_enabled(env) && if (cpu_mips_hw_interrupts_enabled(env) &&
cpu_mips_hw_interrupts_pending(env)) { cpu_mips_hw_interrupts_pending(env)) {

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@ -15566,8 +15566,7 @@ void mips_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb, const TranslationBlock *tb,
const uint64_t *data) const uint64_t *data)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = cpu_env(cs);
CPUMIPSState *env = &cpu->env;
env->active_tc.PC = data[0]; env->active_tc.PC = data[0];
env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags &= ~MIPS_HFLAG_BMASK;