Alpha shadow register optimization
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJV03TlAAoJEK0ScMxN0CebCDUH/jBAivio/oh0MEVOy12uQ+Dm JWyTnde8PHId50ysHwI3+EiE0Jzk1PQv1RV+7RRSy767KOOc+WqRDGaVHN4vjK6Z CgocDUygM79vInaGB34KuvQ0Z+tu4rCIQxBfkCm9OsMF5h/8ZO16IA7RwUQ9GvDj 1KGFL309D4Uw9/oqtx1SQeXwiZR7eI5buaJFfit3uZeaFwyZkkwLXfgvgoPIlvQ+ GMMv5Ejxd5pT/2WwqsxwI0/Y2kxRqyJd0u+28S969Vg0sZ4GlMIsFvjuKqB3kSeZ TpOyNa7ulcywjZotp6OIlr483Sn6SGjzGej/8Qvg5mQ3fxoHTGeQa3NWfvM2+34= =Mg6S -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-axp-201508018' into staging Alpha shadow register optimization # gpg: Signature made Tue 18 Aug 2015 19:09:41 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-axp-201508018: target-alpha: Inline hw_ret target-alpha: Inline call_pal target-alpha: Use separate TCGv temporaries for the shadow registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
4c4a29cb68
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@ -445,8 +445,9 @@ void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
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uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
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void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
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uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
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void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
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#ifndef CONFIG_USER_ONLY
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void swap_shadow_regs(CPUAlphaState *env);
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QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec,
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int unused, unsigned size);
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@ -30,7 +30,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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switch (n) {
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case 0 ... 30:
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val = env->ir[n];
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val = cpu_alpha_load_gr(env, n);
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break;
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case 32 ... 62:
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d.d = env->fir[n - 32];
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@ -66,7 +66,7 @@ int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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switch (n) {
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case 0 ... 30:
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env->ir[n] = tmp;
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cpu_alpha_store_gr(env, n, tmp);
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break;
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case 32 ... 62:
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d.ll = tmp;
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@ -79,6 +79,30 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
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cpu_alpha_store_fpcr(env, val);
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}
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static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg)
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{
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#ifndef CONFIG_USER_ONLY
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if (env->pal_mode) {
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if (reg >= 8 && reg <= 14) {
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return &env->shadow[reg - 8];
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} else if (reg == 25) {
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return &env->shadow[7];
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}
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}
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#endif
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return &env->ir[reg];
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}
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uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg)
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{
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return *cpu_alpha_addr_gr(env, reg);
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}
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void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
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{
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*cpu_alpha_addr_gr(env, reg) = val;
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}
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#if defined(CONFIG_USER_ONLY)
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int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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int rw, int mmu_idx)
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@ -90,38 +114,6 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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return 1;
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}
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#else
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void swap_shadow_regs(CPUAlphaState *env)
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{
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uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
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i0 = env->ir[8];
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i1 = env->ir[9];
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i2 = env->ir[10];
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i3 = env->ir[11];
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i4 = env->ir[12];
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i5 = env->ir[13];
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i6 = env->ir[14];
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i7 = env->ir[25];
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env->ir[8] = env->shadow[0];
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env->ir[9] = env->shadow[1];
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env->ir[10] = env->shadow[2];
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env->ir[11] = env->shadow[3];
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env->ir[12] = env->shadow[4];
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env->ir[13] = env->shadow[5];
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env->ir[14] = env->shadow[6];
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env->ir[25] = env->shadow[7];
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env->shadow[0] = i0;
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env->shadow[1] = i1;
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env->shadow[2] = i2;
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env->shadow[3] = i3;
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env->shadow[4] = i4;
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env->shadow[5] = i5;
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env->shadow[6] = i6;
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env->shadow[7] = i7;
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}
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/* Returns the OSF/1 entMM failure indication, or -1 on success. */
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static int get_physical_address(CPUAlphaState *env, target_ulong addr,
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int prot_need, int mmu_idx,
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@ -375,10 +367,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
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env->pc = env->palbr + i;
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/* Switch to PALmode. */
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if (!env->pal_mode) {
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env->pal_mode = 1;
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swap_shadow_regs(env);
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}
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env->pal_mode = 1;
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#endif /* !USER_ONLY */
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}
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@ -443,7 +432,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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env->pc, env->ps);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
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linux_reg_names[i], env->ir[i]);
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linux_reg_names[i], cpu_alpha_load_gr(env, i));
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if ((i % 3) == 2)
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cpu_fprintf(f, "\n");
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}
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@ -91,9 +91,6 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
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DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
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#if !defined (CONFIG_USER_ONLY)
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DEF_HELPER_2(hw_ret, void, env, i64)
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DEF_HELPER_3(call_pal, void, env, i64, i64)
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DEF_HELPER_2(ldl_phys, i64, env, i64)
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DEF_HELPER_2(ldq_phys, i64, env, i64)
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DEF_HELPER_2(ldl_l_phys, i64, env, i64)
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@ -70,8 +70,8 @@ static VMStateField vmstate_env_fields[] = {
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static const VMStateDescription vmstate_env = {
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.name = "env",
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = vmstate_env_fields,
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};
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@ -40,28 +40,6 @@ uint64_t helper_load_pcc(CPUAlphaState *env)
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/* PALcode support special instructions */
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#ifndef CONFIG_USER_ONLY
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void helper_hw_ret(CPUAlphaState *env, uint64_t a)
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{
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env->pc = a & ~3;
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env->intr_flag = 0;
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env->lock_addr = -1;
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if ((a & 1) == 0) {
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env->pal_mode = 0;
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swap_shadow_regs(env);
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}
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}
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void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
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{
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int pal_mode = env->pal_mode;
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env->exc_addr = pc | pal_mode;
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env->pc = env->palbr + entry_ofs;
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if (!pal_mode) {
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env->pal_mode = 1;
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swap_shadow_regs(env);
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}
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}
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void helper_tbia(CPUAlphaState *env)
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{
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tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
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@ -42,6 +42,9 @@ typedef struct DisasContext DisasContext;
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struct DisasContext {
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struct TranslationBlock *tb;
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uint64_t pc;
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#ifndef CONFIG_USER_ONLY
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uint64_t palbr;
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#endif
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int mem_idx;
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/* Current rounding mode for this TB. */
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@ -52,6 +55,9 @@ struct DisasContext {
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/* implver value for this CPU. */
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int implver;
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/* The set of registers active in the current context. */
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TCGv *ir;
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/* Temporaries for $31 and $f31 as source and destination. */
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TCGv zero;
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TCGv sink;
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@ -86,13 +92,17 @@ typedef enum {
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/* global register indexes */
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static TCGv_ptr cpu_env;
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static TCGv cpu_ir[31];
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static TCGv cpu_std_ir[31];
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static TCGv cpu_fir[31];
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static TCGv cpu_pc;
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static TCGv cpu_lock_addr;
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static TCGv cpu_lock_st_addr;
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static TCGv cpu_lock_value;
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#ifndef CONFIG_USER_ONLY
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static TCGv cpu_pal_ir[31];
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#endif
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#include "exec/gen-icount.h"
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void alpha_translate_init(void)
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@ -122,6 +132,12 @@ void alpha_translate_init(void)
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30"
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};
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#ifndef CONFIG_USER_ONLY
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static const char shadow_names[8][8] = {
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"pal_t7", "pal_s0", "pal_s1", "pal_s2",
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"pal_s3", "pal_s4", "pal_s5", "pal_t11"
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};
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#endif
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static bool done_init = 0;
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int i;
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@ -134,9 +150,9 @@ void alpha_translate_init(void)
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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for (i = 0; i < 31; i++) {
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cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUAlphaState, ir[i]),
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greg_names[i]);
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cpu_std_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUAlphaState, ir[i]),
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greg_names[i]);
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}
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for (i = 0; i < 31; i++) {
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@ -145,6 +161,17 @@ void alpha_translate_init(void)
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freg_names[i]);
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}
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#ifndef CONFIG_USER_ONLY
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memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir));
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for (i = 0; i < 8; i++) {
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int r = (i == 7 ? 25 : i + 8);
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cpu_pal_ir[r] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUAlphaState,
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shadow[i]),
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shadow_names[i]);
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}
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#endif
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for (i = 0; i < ARRAY_SIZE(vars); ++i) {
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const GlobalVar *v = &vars[i];
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*v->var = tcg_global_mem_new_i64(TCG_AREG0, v->ofs, v->name);
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@ -170,7 +197,7 @@ static TCGv dest_sink(DisasContext *ctx)
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static TCGv load_gpr(DisasContext *ctx, unsigned reg)
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{
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if (likely(reg < 31)) {
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return cpu_ir[reg];
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return ctx->ir[reg];
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} else {
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return load_zero(ctx);
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}
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@ -183,7 +210,7 @@ static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg,
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ctx->lit = tcg_const_i64(lit);
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return ctx->lit;
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} else if (likely(reg < 31)) {
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return cpu_ir[reg];
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return ctx->ir[reg];
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} else {
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return load_zero(ctx);
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}
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@ -192,7 +219,7 @@ static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg,
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static TCGv dest_gpr(DisasContext *ctx, unsigned reg)
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{
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if (likely(reg < 31)) {
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return cpu_ir[reg];
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return ctx->ir[reg];
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} else {
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return dest_sink(ctx);
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}
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@ -304,7 +331,7 @@ static inline void gen_load_mem(DisasContext *ctx,
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addr = tmp;
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}
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va = (fp ? cpu_fir[ra] : cpu_ir[ra]);
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va = (fp ? cpu_fir[ra] : ctx->ir[ra]);
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tcg_gen_qemu_load(va, addr, ctx->mem_idx);
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tcg_temp_free(tmp);
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@ -399,13 +426,13 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb,
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tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, quad ? MO_LEQ : MO_LESL);
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tcg_gen_brcond_i64(TCG_COND_NE, val, cpu_lock_value, lab_fail);
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tcg_gen_qemu_st_i64(cpu_ir[ra], addr, ctx->mem_idx,
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tcg_gen_qemu_st_i64(ctx->ir[ra], addr, ctx->mem_idx,
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quad ? MO_LEQ : MO_LEUL);
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tcg_gen_movi_i64(cpu_ir[ra], 1);
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tcg_gen_movi_i64(ctx->ir[ra], 1);
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tcg_gen_br(lab_done);
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gen_set_label(lab_fail);
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tcg_gen_movi_i64(cpu_ir[ra], 0);
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tcg_gen_movi_i64(ctx->ir[ra], 0);
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gen_set_label(lab_done);
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tcg_gen_movi_i64(cpu_lock_addr, -1);
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@ -444,7 +471,7 @@ static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp)
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uint64_t dest = ctx->pc + (disp << 2);
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if (ra != 31) {
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tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
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tcg_gen_movi_i64(ctx->ir[ra], ctx->pc);
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}
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/* Notice branch-to-next; used to initialize RA with the PC. */
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@ -1059,12 +1086,13 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
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}
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}
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static void gen_rx(int ra, int set)
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static void gen_rx(DisasContext *ctx, int ra, int set)
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{
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TCGv_i32 tmp;
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if (ra != 31) {
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tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, intr_flag));
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tcg_gen_ld8u_i64(ctx->ir[ra], cpu_env,
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offsetof(CPUAlphaState, intr_flag));
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}
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tmp = tcg_const_i32(set);
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@ -1086,12 +1114,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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break;
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case 0x9E:
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/* RDUNIQUE */
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tcg_gen_ld_i64(cpu_ir[IR_V0], cpu_env,
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tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
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offsetof(CPUAlphaState, unique));
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break;
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case 0x9F:
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/* WRUNIQUE */
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tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
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tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
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offsetof(CPUAlphaState, unique));
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break;
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default:
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@ -1115,17 +1143,17 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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break;
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case 0x2D:
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/* WRVPTPTR */
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tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
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tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
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offsetof(CPUAlphaState, vptptr));
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break;
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case 0x31:
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/* WRVAL */
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tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
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tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
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offsetof(CPUAlphaState, sysval));
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break;
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case 0x32:
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/* RDVAL */
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tcg_gen_ld_i64(cpu_ir[IR_V0], cpu_env,
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tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
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offsetof(CPUAlphaState, sysval));
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break;
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@ -1135,12 +1163,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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/* Note that we already know we're in kernel mode, so we know
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that PS only contains the 3 IPL bits. */
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tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env,
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tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env,
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offsetof(CPUAlphaState, ps));
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/* But make sure and store only the 3 IPL bits from the user. */
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tmp = tcg_temp_new();
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tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK);
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tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK);
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tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps));
|
||||
tcg_temp_free(tmp);
|
||||
break;
|
||||
|
|
@ -1148,22 +1176,22 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
|
|||
|
||||
case 0x36:
|
||||
/* RDPS */
|
||||
tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env,
|
||||
tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env,
|
||||
offsetof(CPUAlphaState, ps));
|
||||
break;
|
||||
case 0x38:
|
||||
/* WRUSP */
|
||||
tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
|
||||
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
|
||||
offsetof(CPUAlphaState, usp));
|
||||
break;
|
||||
case 0x3A:
|
||||
/* RDUSP */
|
||||
tcg_gen_ld_i64(cpu_ir[IR_V0], cpu_env,
|
||||
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
|
||||
offsetof(CPUAlphaState, usp));
|
||||
break;
|
||||
case 0x3C:
|
||||
/* WHAMI */
|
||||
tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
|
||||
tcg_gen_ld32s_i64(ctx->ir[IR_V0], cpu_env,
|
||||
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
|
||||
break;
|
||||
|
||||
|
|
@ -1181,15 +1209,24 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
|
|||
return gen_excp(ctx, EXCP_CALL_PAL, palcode);
|
||||
#else
|
||||
{
|
||||
TCGv pc = tcg_const_i64(ctx->pc);
|
||||
TCGv entry = tcg_const_i64(palcode & 0x80
|
||||
? 0x2000 + (palcode - 0x80) * 64
|
||||
: 0x1000 + palcode * 64);
|
||||
TCGv tmp = tcg_temp_new();
|
||||
uint64_t exc_addr = ctx->pc;
|
||||
uint64_t entry = ctx->palbr;
|
||||
|
||||
gen_helper_call_pal(cpu_env, pc, entry);
|
||||
if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
||||
exc_addr |= 1;
|
||||
} else {
|
||||
tcg_gen_movi_i64(tmp, 1);
|
||||
tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode));
|
||||
}
|
||||
|
||||
tcg_temp_free(entry);
|
||||
tcg_temp_free(pc);
|
||||
tcg_gen_movi_i64(tmp, exc_addr);
|
||||
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
|
||||
tcg_temp_free(tmp);
|
||||
|
||||
entry += (palcode & 0x80
|
||||
? 0x2000 + (palcode - 0x80) * 64
|
||||
: 0x1000 + palcode * 64);
|
||||
|
||||
/* Since the destination is running in PALmode, we don't really
|
||||
need the page permissions check. We'll see the existence of
|
||||
|
|
@ -1197,11 +1234,13 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
|
|||
we change the PAL base register. */
|
||||
if (!ctx->singlestep_enabled && !(ctx->tb->cflags & CF_LAST_IO)) {
|
||||
tcg_gen_goto_tb(0);
|
||||
tcg_gen_movi_i64(cpu_pc, entry);
|
||||
tcg_gen_exit_tb((uintptr_t)ctx->tb);
|
||||
return EXIT_GOTO_TB;
|
||||
} else {
|
||||
tcg_gen_movi_i64(cpu_pc, entry);
|
||||
return EXIT_PC_UPDATED;
|
||||
}
|
||||
|
||||
return EXIT_PC_UPDATED;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1228,8 +1267,6 @@ static int cpu_pr_data(int pr)
|
|||
case 11: return offsetof(CPUAlphaState, sysval);
|
||||
case 12: return offsetof(CPUAlphaState, usp);
|
||||
|
||||
case 32 ... 39:
|
||||
return offsetof(CPUAlphaState, shadow[pr - 32]);
|
||||
case 40 ... 63:
|
||||
return offsetof(CPUAlphaState, scratch[pr - 40]);
|
||||
|
||||
|
|
@ -1241,36 +1278,48 @@ static int cpu_pr_data(int pr)
|
|||
|
||||
static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)
|
||||
{
|
||||
int data = cpu_pr_data(regno);
|
||||
void (*helper)(TCGv);
|
||||
int data;
|
||||
|
||||
/* Special help for VMTIME and WALLTIME. */
|
||||
if (regno == 250 || regno == 249) {
|
||||
void (*helper)(TCGv) = gen_helper_get_walltime;
|
||||
if (regno == 249) {
|
||||
helper = gen_helper_get_vmtime;
|
||||
}
|
||||
if (ctx->tb->cflags & CF_USE_ICOUNT) {
|
||||
switch (regno) {
|
||||
case 32 ... 39:
|
||||
/* Accessing the "non-shadow" general registers. */
|
||||
regno = regno == 39 ? 25 : regno - 32 + 8;
|
||||
tcg_gen_mov_i64(va, cpu_std_ir[regno]);
|
||||
break;
|
||||
|
||||
case 250: /* WALLTIME */
|
||||
helper = gen_helper_get_walltime;
|
||||
goto do_helper;
|
||||
case 249: /* VMTIME */
|
||||
helper = gen_helper_get_vmtime;
|
||||
do_helper:
|
||||
if (use_icount) {
|
||||
gen_io_start();
|
||||
helper(va);
|
||||
gen_io_end();
|
||||
return EXIT_PC_STALE;
|
||||
} else {
|
||||
helper(va);
|
||||
return NO_EXIT;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* The basic registers are data only, and unknown registers
|
||||
are read-zero, write-ignore. */
|
||||
data = cpu_pr_data(regno);
|
||||
if (data == 0) {
|
||||
tcg_gen_movi_i64(va, 0);
|
||||
} else if (data & PR_BYTE) {
|
||||
tcg_gen_ld8u_i64(va, cpu_env, data & ~PR_BYTE);
|
||||
} else if (data & PR_LONG) {
|
||||
tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG);
|
||||
} else {
|
||||
tcg_gen_ld_i64(va, cpu_env, data);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* The basic registers are data only, and unknown registers
|
||||
are read-zero, write-ignore. */
|
||||
if (data == 0) {
|
||||
tcg_gen_movi_i64(va, 0);
|
||||
} else if (data & PR_BYTE) {
|
||||
tcg_gen_ld8u_i64(va, cpu_env, data & ~PR_BYTE);
|
||||
} else if (data & PR_LONG) {
|
||||
tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG);
|
||||
} else {
|
||||
tcg_gen_ld_i64(va, cpu_env, data);
|
||||
}
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
|
|
@ -1316,6 +1365,12 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
|
|||
gen_helper_tb_flush(cpu_env);
|
||||
return EXIT_PC_STALE;
|
||||
|
||||
case 32 ... 39:
|
||||
/* Accessing the "non-shadow" general registers. */
|
||||
regno = regno == 39 ? 25 : regno - 32 + 8;
|
||||
tcg_gen_mov_i64(cpu_std_ir[regno], vb);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* The basic registers are data only, and unknown registers
|
||||
are read-zero, write-ignore. */
|
||||
|
|
@ -2295,14 +2350,14 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
break;
|
||||
case 0xE000:
|
||||
/* RC */
|
||||
gen_rx(ra, 0);
|
||||
gen_rx(ctx, ra, 0);
|
||||
break;
|
||||
case 0xE800:
|
||||
/* ECB */
|
||||
break;
|
||||
case 0xF000:
|
||||
/* RS */
|
||||
gen_rx(ra, 1);
|
||||
gen_rx(ctx, ra, 1);
|
||||
break;
|
||||
case 0xF800:
|
||||
/* WH64 */
|
||||
|
|
@ -2334,7 +2389,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
vb = load_gpr(ctx, rb);
|
||||
tcg_gen_andi_i64(cpu_pc, vb, ~3);
|
||||
if (ra != 31) {
|
||||
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
|
||||
tcg_gen_movi_i64(ctx->ir[ra], ctx->pc);
|
||||
}
|
||||
ret = EXIT_PC_UPDATED;
|
||||
break;
|
||||
|
|
@ -2374,10 +2429,10 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
goto invalid_opc;
|
||||
break;
|
||||
case 0x6:
|
||||
/* Incpu_ir[ra]id */
|
||||
/* Invalid */
|
||||
goto invalid_opc;
|
||||
case 0x7:
|
||||
/* Incpu_ir[ra]id */
|
||||
/* Invaliid */
|
||||
goto invalid_opc;
|
||||
case 0x8:
|
||||
/* Longword virtual access (hw_ldl) */
|
||||
|
|
@ -2580,13 +2635,18 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
/* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
|
||||
address from EXC_ADDR. This turns out to be useful for our
|
||||
emulation PALcode, so continue to accept it. */
|
||||
tmp = tcg_temp_new();
|
||||
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
|
||||
gen_helper_hw_ret(cpu_env, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
ctx->lit = vb = tcg_temp_new();
|
||||
tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr));
|
||||
} else {
|
||||
gen_helper_hw_ret(cpu_env, load_gpr(ctx, rb));
|
||||
vb = load_gpr(ctx, rb);
|
||||
}
|
||||
tmp = tcg_temp_new();
|
||||
tcg_gen_movi_i64(tmp, 0);
|
||||
tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag));
|
||||
tcg_gen_movi_i64(cpu_lock_addr, -1);
|
||||
tcg_gen_andi_i64(tmp, vb, 1);
|
||||
tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode));
|
||||
tcg_gen_andi_i64(cpu_pc, vb, ~3);
|
||||
ret = EXIT_PC_UPDATED;
|
||||
break;
|
||||
#else
|
||||
|
|
@ -2817,6 +2877,13 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
|
|||
ctx.implver = env->implver;
|
||||
ctx.singlestep_enabled = cs->singlestep_enabled;
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
ctx.ir = cpu_std_ir;
|
||||
#else
|
||||
ctx.palbr = env->palbr;
|
||||
ctx.ir = (tb->flags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
|
||||
#endif
|
||||
|
||||
/* ??? Every TB begins with unset rounding mode, to be initialized on
|
||||
the first fp insn of the TB. Alternately we could define a proper
|
||||
default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
|
||||
|
|
|
|||
Loading…
Reference in New Issue