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Hexagon (target/hexagon) Analyze packet for HVX 

Extend the analyze_<tag> functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
    fugure_VRegs and tmp_VRegs

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-8-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-03-06 18:58:21 -08:00
parent 4d13bb51d2
commit 4d6f84208c
4 changed files with 52 additions and 27 deletions
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17
target/hexagon/gen_analyze_funcs.py
View File

@ -83,9 +83,16 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
newv = "EXT_DFL"
if (hex_common.is_new_result(tag)):
newv = "EXT_NEW"
elif (hex_common.is_tmp_result(tag)):
newv = "EXT_TMP"
if (regid in {"dd", "xx"}):
f.write("// const int %s = insn->regno[%d];\n" %\
f.write(" const int %s = insn->regno[%d];\n" %\
(regN, regno))
f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
elif (regid in {"uu", "vv"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
@ -93,14 +100,18 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d", "x", "y"}):
f.write("// const int %s = insn->regno[%d];\n" % \
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write("// const int %s = insn->regno[%d];\n" % \
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \
(regN, predicated))
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))

18
target/hexagon/gen_tcg_funcs.py
View File

@ -152,17 +152,6 @@ def genptr_decl(f, tag, regtype, regid, regno):
f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
(regtype, regid))
f.write(" 1, true);\n");
if 'A_CONDEXEC' in hex_common.attribdict[tag]:
f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN))
f.write(" intptr_t src_off =")
f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \
(regtype, regid))
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" src_off,\n")
f.write(" sizeof(MMVector),\n")
f.write(" sizeof(MMVector));\n")
f.write(" }\n")
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
@ -421,9 +410,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
(regtype, regid, regtype, regid))
f.write("%s, insn->slot, %s);\n" % \
(newv, is_predicated))
f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \
(regtype, regid, newv))
f.write(" %s);\n" % (is_predicated))
elif (regid in {"d", "x", "y"}):
if ('A_CONDEXEC' in hex_common.attribdict[tag]):
is_predicated = "true"
@ -433,8 +419,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
(regtype, regid, regtype, regid, newv))
f.write("insn->slot, %s);\n" % \
(is_predicated))
f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \
(regtype, regid, newv, is_predicated))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
@ -446,8 +430,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \
(regtype, regid, regtype, regid, newv))
f.write("insn->slot, %s);\n" % (is_predicated))
f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \
(regtype, regid, is_predicated))
else:
print("Bad register parse: ", regtype, regid)
else:

30
target/hexagon/translate.c
View File

@ -364,6 +364,8 @@ static void gen_start_packet(DisasContext *ctx)
bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
bitmap_zero(ctx->vregs_updated, NUM_VREGS);
bitmap_zero(ctx->vregs_select, NUM_VREGS);
bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
ctx->qreg_log_idx = 0;
for (i = 0; i < STORES_MAX; i++) {
ctx->store_width[i] = 0;
@ -415,6 +417,34 @@ static void gen_start_packet(DisasContext *ctx)
}
}
/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, i, 1, true);
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
tcg_gen_gvec_mov(MO_64, VdV_off,
src_off,
sizeof(MMVector),
sizeof(MMVector));
i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1);
}
}
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_tmp_vreg_off(ctx, i, 1, true);
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
tcg_gen_gvec_mov(MO_64, VdV_off,
src_off,
sizeof(MMVector),
sizeof(MMVector));
i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1);
}
}
if (pkt->pkt_has_hvx) {
tcg_gen_movi_tl(hex_VRegs_updated, 0);
tcg_gen_movi_tl(hex_QRegs_updated, 0);

14
target/hexagon/translate.h
View File

@ -54,6 +54,8 @@ typedef struct DisasContext {
DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
DECLARE_BITMAP(vregs_updated, NUM_VREGS);
DECLARE_BITMAP(vregs_select, NUM_VREGS);
DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
int qreg_log[NUM_QREGS];
bool qreg_is_predicated[NUM_QREGS];
int qreg_log_idx;
@ -99,12 +101,6 @@ static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
ctx_log_reg_write(ctx, rnum + 1, is_predicated);
}
static inline bool is_vreg_preloaded(DisasContext *ctx, int num)
{
return test_bit(num, ctx->vregs_updated) ||
test_bit(num, ctx->vregs_updated_tmp);
}
intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
int num, bool alloc_ok);
intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
@ -120,12 +116,18 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
ctx->vreg_log_idx++;
set_bit(rnum, ctx->vregs_updated);
if (is_predicated) {
set_bit(rnum, ctx->predicated_future_vregs);
}
}
if (type == EXT_NEW) {
set_bit(rnum, ctx->vregs_select);
}
if (type == EXT_TMP) {
set_bit(rnum, ctx->vregs_updated_tmp);
if (is_predicated) {
set_bit(rnum, ctx->predicated_tmp_vregs);
}
}
}