Hexagon (target/hexagon) Analyze packet for HVX
Extend the analyze_<tag> functions for HVX vector and predicate writes Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py During gen_start_packet, reload the predicated HVX registers into fugure_VRegs and tmp_VRegs Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-8-tsimpson@quicinc.com>
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@ -83,9 +83,16 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "V"):
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newv = "EXT_DFL"
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if (hex_common.is_new_result(tag)):
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newv = "EXT_NEW"
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elif (hex_common.is_tmp_result(tag)):
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newv = "EXT_TMP"
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if (regid in {"dd", "xx"}):
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f.write("// const int %s = insn->regno[%d];\n" %\
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f.write(" const int %s = insn->regno[%d];\n" %\
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(regN, regno))
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f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
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(regN, newv, predicated))
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elif (regid in {"uu", "vv"}):
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f.write("// const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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@ -93,14 +100,18 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
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f.write("// const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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elif (regid in {"d", "x", "y"}):
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f.write("// const int %s = insn->regno[%d];\n" % \
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f.write(" const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
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(regN, newv, predicated))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "x"}):
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f.write("// const int %s = insn->regno[%d];\n" % \
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f.write(" const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \
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(regN, predicated))
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elif (regid in {"s", "t", "u", "v"}):
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f.write("// const int %s = insn->regno[%d];\n" % \
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(regN, regno))
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@ -152,17 +152,6 @@ def genptr_decl(f, tag, regtype, regid, regno):
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f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
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(regtype, regid))
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f.write(" 1, true);\n");
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if 'A_CONDEXEC' in hex_common.attribdict[tag]:
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f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN))
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f.write(" intptr_t src_off =")
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f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \
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(regtype, regid))
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f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
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(regtype, regid))
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f.write(" src_off,\n")
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f.write(" sizeof(MMVector),\n")
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f.write(" sizeof(MMVector));\n")
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f.write(" }\n")
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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@ -421,9 +410,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
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(regtype, regid, regtype, regid))
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f.write("%s, insn->slot, %s);\n" % \
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(newv, is_predicated))
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f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \
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(regtype, regid, newv))
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f.write(" %s);\n" % (is_predicated))
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elif (regid in {"d", "x", "y"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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@ -433,8 +419,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % \
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(is_predicated))
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f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \
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(regtype, regid, newv, is_predicated))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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@ -446,8 +430,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
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f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % (is_predicated))
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f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \
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(regtype, regid, is_predicated))
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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@ -364,6 +364,8 @@ static void gen_start_packet(DisasContext *ctx)
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bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
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bitmap_zero(ctx->vregs_updated, NUM_VREGS);
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bitmap_zero(ctx->vregs_select, NUM_VREGS);
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bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
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bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
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ctx->qreg_log_idx = 0;
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for (i = 0; i < STORES_MAX; i++) {
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ctx->store_width[i] = 0;
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@ -415,6 +417,34 @@ static void gen_start_packet(DisasContext *ctx)
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}
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}
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/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
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if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
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int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
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while (i < NUM_VREGS) {
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const intptr_t VdV_off =
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ctx_future_vreg_off(ctx, i, 1, true);
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intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
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tcg_gen_gvec_mov(MO_64, VdV_off,
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src_off,
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sizeof(MMVector),
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sizeof(MMVector));
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i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1);
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}
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}
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if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
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int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
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while (i < NUM_VREGS) {
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const intptr_t VdV_off =
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ctx_tmp_vreg_off(ctx, i, 1, true);
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intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
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tcg_gen_gvec_mov(MO_64, VdV_off,
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src_off,
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sizeof(MMVector),
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sizeof(MMVector));
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i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1);
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}
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}
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if (pkt->pkt_has_hvx) {
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tcg_gen_movi_tl(hex_VRegs_updated, 0);
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tcg_gen_movi_tl(hex_QRegs_updated, 0);
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@ -54,6 +54,8 @@ typedef struct DisasContext {
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DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated, NUM_VREGS);
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DECLARE_BITMAP(vregs_select, NUM_VREGS);
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DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
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DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
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int qreg_log[NUM_QREGS];
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bool qreg_is_predicated[NUM_QREGS];
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int qreg_log_idx;
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@ -99,12 +101,6 @@ static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
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ctx_log_reg_write(ctx, rnum + 1, is_predicated);
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}
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static inline bool is_vreg_preloaded(DisasContext *ctx, int num)
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{
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return test_bit(num, ctx->vregs_updated) ||
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test_bit(num, ctx->vregs_updated_tmp);
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}
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intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok);
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intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
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@ -120,12 +116,18 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
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ctx->vreg_log_idx++;
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set_bit(rnum, ctx->vregs_updated);
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if (is_predicated) {
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set_bit(rnum, ctx->predicated_future_vregs);
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}
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}
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if (type == EXT_NEW) {
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set_bit(rnum, ctx->vregs_select);
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}
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if (type == EXT_TMP) {
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set_bit(rnum, ctx->vregs_updated_tmp);
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if (is_predicated) {
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set_bit(rnum, ctx->predicated_tmp_vregs);
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}
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}
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}
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