target-i386: make cpu-qom.h not target specific
Make X86CPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini
parent
28618ac652
commit
4da6f8d954
@ -67,101 +67,6 @@ typedef struct X86CPUClass {
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void (*parent_reset)(CPUState *cpu);
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} X86CPUClass;
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/**
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* X86CPU:
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* @env: #CPUX86State
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* @migratable: If set, only migratable flags will be accepted when "enforce"
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* mode is used, and only migratable flags will be included in the "host"
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* CPU model.
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*
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* An x86 CPU.
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*/
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typedef struct X86CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUX86State env;
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bool hyperv_vapic;
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bool hyperv_relaxed_timing;
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int hyperv_spinlock_attempts;
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char *hyperv_vendor_id;
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bool hyperv_time;
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bool hyperv_crash;
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bool hyperv_reset;
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bool hyperv_vpindex;
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bool hyperv_runtime;
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bool hyperv_synic;
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bool hyperv_stimer;
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bool check_cpuid;
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bool enforce_cpuid;
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bool expose_kvm;
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bool migratable;
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bool host_features;
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int64_t apic_id;
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/* if true the CPUID code directly forward host cache leaves to the guest */
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bool cache_info_passthrough;
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/* Features that were filtered out because of missing host capabilities */
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uint32_t filtered_features[FEATURE_WORDS];
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/* Enable PMU CPUID bits. This can't be enabled by default yet because
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* it doesn't have ABI stability guarantees, as it passes all PMU CPUID
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* bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
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* capabilities) directly to the guest.
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*/
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bool enable_pmu;
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/* in order to simplify APIC support, we leave this pointer to the
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user */
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struct DeviceState *apic_state;
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struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
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Notifier machine_done;
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} X86CPU;
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static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
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{
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return container_of(env, X86CPU, env);
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}
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#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
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#define ENV_OFFSET offsetof(X86CPU, env)
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#ifndef CONFIG_USER_ONLY
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extern struct VMStateDescription vmstate_x86_cpu;
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#endif
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/**
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* x86_cpu_do_interrupt:
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* @cpu: vCPU the interrupt is to be handled by.
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*/
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void x86_cpu_do_interrupt(CPUState *cpu);
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bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void x86_cpu_exec_enter(CPUState *cpu);
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void x86_cpu_exec_exit(CPUState *cpu);
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typedef struct X86CPU X86CPU;
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#endif
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@ -20,6 +20,7 @@
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#define CPU_I386_H
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#include "qemu-common.h"
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#include "cpu-qom.h"
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#include "standard-headers/asm-x86/hyperv.h"
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#ifdef TARGET_X86_64
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@ -1028,7 +1029,102 @@ typedef struct CPUX86State {
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TPRAccess tpr_access_type;
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} CPUX86State;
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#include "cpu-qom.h"
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/**
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* X86CPU:
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* @env: #CPUX86State
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* @migratable: If set, only migratable flags will be accepted when "enforce"
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* mode is used, and only migratable flags will be included in the "host"
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* CPU model.
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*
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* An x86 CPU.
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*/
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struct X86CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUX86State env;
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bool hyperv_vapic;
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bool hyperv_relaxed_timing;
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int hyperv_spinlock_attempts;
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char *hyperv_vendor_id;
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bool hyperv_time;
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bool hyperv_crash;
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bool hyperv_reset;
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bool hyperv_vpindex;
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bool hyperv_runtime;
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bool hyperv_synic;
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bool hyperv_stimer;
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bool check_cpuid;
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bool enforce_cpuid;
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bool expose_kvm;
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bool migratable;
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bool host_features;
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int64_t apic_id;
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/* if true the CPUID code directly forward host cache leaves to the guest */
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bool cache_info_passthrough;
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/* Features that were filtered out because of missing host capabilities */
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uint32_t filtered_features[FEATURE_WORDS];
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/* Enable PMU CPUID bits. This can't be enabled by default yet because
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* it doesn't have ABI stability guarantees, as it passes all PMU CPUID
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* bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
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* capabilities) directly to the guest.
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*/
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bool enable_pmu;
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/* in order to simplify APIC support, we leave this pointer to the
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user */
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struct DeviceState *apic_state;
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struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
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Notifier machine_done;
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};
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static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
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{
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return container_of(env, X86CPU, env);
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}
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#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
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#define ENV_OFFSET offsetof(X86CPU, env)
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#ifndef CONFIG_USER_ONLY
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extern struct VMStateDescription vmstate_x86_cpu;
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#endif
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/**
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* x86_cpu_do_interrupt:
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* @cpu: vCPU the interrupt is to be handled by.
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*/
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void x86_cpu_do_interrupt(CPUState *cpu);
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bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void x86_cpu_exec_enter(CPUState *cpu);
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void x86_cpu_exec_exit(CPUState *cpu);
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X86CPU *cpu_x86_init(const char *cpu_model);
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X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
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