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target/riscv: Remove condition guarding register zero for auipc and lui

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Commit 57c108b864 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Víctor Colombo 2022-06-10 13:55:17 -03:00 committed by Alistair Francis
parent d495e432c0
commit 4e245a9e26
1 changed files with 2 additions and 6 deletions
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8
target/riscv/insn_trans/trans_rvi.c.inc
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@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
gen_set_gpri(ctx, a->rd, a->imm);
}
gen_set_gpri(ctx, a->rd, a->imm);
return true;
}
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
}
gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
return true;
}