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target/tricore: Add shuffle insn

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this is based on code by volumit (https://github.com/volumit/qemu/).

Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
and https://gitlab.com/qemu-project/qemu/-/issues/1452.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-7-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-06-14 12:00:37 +02:00
parent 0eaafe33d0
commit 4e3377bb5a
4 changed files with 46 additions and 0 deletions
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1
target/tricore/helper.h
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@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)

36
target/tricore/op_helper.c
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@ -2308,6 +2308,42 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
{
uint32_t resb;
uint32_t byte_select;
uint32_t res = 0;
byte_select = arg1 & 0x3;
resb = extract32(arg0, byte_select * 8, 8);
res |= resb << 0;
byte_select = (arg1 >> 2) & 0x3;
resb = extract32(arg0, byte_select * 8, 8);
res |= resb << 8;
byte_select = (arg1 >> 4) & 0x3;
resb = extract32(arg0, byte_select * 8, 8);
res |= resb << 16;
byte_select = (arg1 >> 6) & 0x3;
resb = extract32(arg0, byte_select * 8, 8);
res |= resb << 24;
if (arg1 & 0x100) {
/* Assign the correct nibble position. */
res = ((res & 0xf0f0f0f0) >> 4)
| ((res & 0x0f0f0f0f) << 4);
/* Assign the correct bit position. */
res = ((res & 0x88888888) >> 3)
| ((res & 0x44444444) >> 1)
| ((res & 0x22222222) << 1)
| ((res & 0x11111111) << 3);
}
return res;
}
/* context save area (CSA) related helpers */
static int cdc_increment(target_ulong *psw)

8
target/tricore/translate.c
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@ -5011,6 +5011,14 @@ static void decode_rc_logical_shift(DisasContext *ctx)
case OPC2_32_RC_XOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SHUFFLE:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
TCGv temp = tcg_constant_i32(const9);
gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}

1
target/tricore/tricore-opcodes.h
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@ -885,6 +885,7 @@ enum {
OPC2_32_RC_SHAS = 0x02,
OPC2_32_RC_XNOR = 0x0d,
OPC2_32_RC_XOR = 0x0c,
OPC2_32_RC_SHUFFLE = 0x07, /* v1.6.2 only */
};
/* OPCM_32_RC_ACCUMULATOR */
enum {