linux-user/sparc: Handle floating-point exceptions
Raise SIGFPE for ieee exceptions. The other types, such as FSR_FTT_UNIMPFPOP, should not appear, because we enable normal emulation of missing insns at the start of sparc_cpu_realizefn(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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@ -297,6 +297,28 @@ void cpu_loop (CPUSPARCState *env)
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restore_window(env);
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break;
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case TT_FP_EXCP:
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{
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int code = TARGET_FPE_FLTUNK;
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target_ulong fsr = env->fsr;
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if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) {
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if (fsr & FSR_NVC) {
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code = TARGET_FPE_FLTINV;
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} else if (fsr & FSR_OFC) {
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code = TARGET_FPE_FLTOVF;
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} else if (fsr & FSR_UFC) {
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code = TARGET_FPE_FLTUND;
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} else if (fsr & FSR_DZC) {
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code = TARGET_FPE_FLTDIV;
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} else if (fsr & FSR_NXC) {
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code = TARGET_FPE_FLTRES;
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}
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}
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force_sig_fault(TARGET_SIGFPE, code, env->pc);
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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@ -197,8 +197,7 @@ enum {
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#define FSR_FTT2 (1ULL << 16)
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#define FSR_FTT1 (1ULL << 15)
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#define FSR_FTT0 (1ULL << 14)
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//gcc warns about constant overflow for ~FSR_FTT_MASK
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//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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#ifdef TARGET_SPARC64
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#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
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#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
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