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RISC-V Patches for 4.2-rc3 

This tag contains two patches that I'd like to target for 4.2-rc3:
 
 * A fix to the DT entry for the SiFive test finisher.
 * A fix to the spike board's HTIF interface.
 
 This passes "make check" and boots OE for me.
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging

RISC-V Patches for 4.2-rc3

This tag contains two patches that I'd like to target for 4.2-rc3:

* A fix to the DT entry for the SiFive test finisher.
* A fix to the spike board's HTIF interface.

This passes "make check" and boots OE for me.

# gpg: Signature made Mon 25 Nov 2019 20:51:13 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-rc3:
  hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()
  RISC-V: virt: This is a "sifive,test1" test finisher

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-11-26 12:36:40 +00:00
parent a5f80c16f2 6478dd745d
commit 4ecc984210
6 changed files with 18 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/riscv/boot.c
View File

@ -114,12 +114,13 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1);
}
target_ulong riscv_load_kernel(const char *kernel_filename)
target_ulong riscv_load_kernel(const char *kernel_filename, symbol_fn_t sym_cb)
{
uint64_t kernel_entry, kernel_high;
if (load_elf(kernel_filename, NULL, NULL, NULL,
&kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
&kernel_entry, NULL, &kernel_high, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
return kernel_entry;
}

2
hw/riscv/sifive_e.c
View File

@ -111,7 +111,7 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
riscv_load_kernel(machine->kernel_filename, NULL);
}
}

3
hw/riscv/sifive_u.c
View File

@ -344,7 +344,8 @@ static void riscv_sifive_u_init(MachineState *machine)
memmap[SIFIVE_U_DRAM].base);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
NULL);
if (machine->initrd_filename) {
hwaddr start;

6
hw/riscv/spike.c
View File

@ -184,7 +184,7 @@ static void spike_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
}
/* reset vector */
@ -273,7 +273,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
}
/* reset vector */
@ -359,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
}
/* reset vector */

8
hw/riscv/virt.c
View File

@ -359,7 +359,10 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
nodename = g_strdup_printf("/test@%lx",
(long)memmap[VIRT_TEST].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
{
const char compat[] = "sifive,test1\0sifive,test0";
qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
}
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[VIRT_TEST].base,
0x0, memmap[VIRT_TEST].size);
@ -476,7 +479,8 @@ static void riscv_virt_board_init(MachineState *machine)
memmap[VIRT_DRAM].base);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
NULL);
if (machine->initrd_filename) {
hwaddr start;

3
include/hw/riscv/boot.h
View File

@ -28,7 +28,8 @@ void riscv_find_and_load_firmware(MachineState *machine,
char *riscv_find_firmware(const char *firmware_filename);
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr);
target_ulong riscv_load_kernel(const char *kernel_filename);
target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);