sii3112: Remove duplicated code and use PCI IDE ops instead
Parts of the SiI3112 mmio are identical to PCI IDE registers so we can use the corresponding functions that were factored out into ide/pci.c. This removes code duplication and simplifies the SiI3112 model which also helped to spot a copy paste error where reading status of the 2nd channel read the 1st channel instead. This is also fixed here. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 793b6a7934ef2bba26b8d066bec446019efa6c5d.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
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@ -88,35 +88,19 @@ static uint64_t sii3112_reg_read(void *opaque, hwaddr addr,
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val |= (uint32_t)d->i.bmdma[1].status << 16;
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break;
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case 0x80 ... 0x87:
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if (size == 1) {
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val = ide_ioport_read(&d->i.bus[0], addr - 0x80);
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} else if (addr == 0x80) {
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val = (size == 2) ? ide_data_readw(&d->i.bus[0], 0) :
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ide_data_readl(&d->i.bus[0], 0);
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} else {
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val = (1ULL << (size * 8)) - 1;
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}
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val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size);
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break;
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case 0x8a:
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val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
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(1ULL << (size * 8)) - 1;
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val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size);
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break;
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case 0xa0:
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val = d->regs[0].confstat;
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break;
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case 0xc0 ... 0xc7:
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if (size == 1) {
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val = ide_ioport_read(&d->i.bus[1], addr - 0xc0);
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} else if (addr == 0xc0) {
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val = (size == 2) ? ide_data_readw(&d->i.bus[1], 0) :
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ide_data_readl(&d->i.bus[1], 0);
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} else {
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val = (1ULL << (size * 8)) - 1;
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}
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val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size);
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break;
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case 0xca:
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val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
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(1ULL << (size * 8)) - 1;
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val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size);
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break;
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case 0xe0:
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val = d->regs[1].confstat;
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@ -186,36 +170,16 @@ static void sii3112_reg_write(void *opaque, hwaddr addr,
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bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
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break;
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case 0x80 ... 0x87:
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if (size == 1) {
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ide_ioport_write(&d->i.bus[0], addr - 0x80, val);
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} else if (addr == 0x80) {
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if (size == 2) {
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ide_data_writew(&d->i.bus[0], 0, val);
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} else {
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ide_data_writel(&d->i.bus[0], 0, val);
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}
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}
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pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size);
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break;
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case 0x8a:
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if (size == 1) {
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ide_cmd_write(&d->i.bus[0], 4, val);
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}
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pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size);
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break;
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case 0xc0 ... 0xc7:
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if (size == 1) {
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ide_ioport_write(&d->i.bus[1], addr - 0xc0, val);
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} else if (addr == 0xc0) {
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if (size == 2) {
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ide_data_writew(&d->i.bus[1], 0, val);
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} else {
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ide_data_writel(&d->i.bus[1], 0, val);
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}
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}
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pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size);
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break;
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case 0xca:
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if (size == 1) {
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ide_cmd_write(&d->i.bus[1], 4, val);
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}
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pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size);
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break;
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case 0x100:
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d->regs[0].scontrol = val & 0xfff;
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