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target/riscv: add RVG and remove cpu->cfg.ext_g

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We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
and use riscv_has_ext(env, RVG).

The caveat is that we don't have RVG, so add it. RVG will be used right
off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
enabling G via the now removed 'ext_g' flag.

After this patch, there are no more MISA extensions represented by flags
in RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:50 -03:00 committed by Alistair Francis
parent 8ef67c6637
commit 4f13abcb2b
2 changed files with 9 additions and 10 deletions
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17
target/riscv/cpu.c
View File

@ -403,10 +403,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVC | RVS | RVU);
set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;
@ -814,12 +813,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
if (riscv_has_ext(env, RVG) &&
!(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@ -1462,6 +1460,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVJ, .enabled = false},
{.name = "v", .description = "Vector operations",
.misa_bit = RVV, .enabled = false},
{.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)",
.misa_bit = RVG, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1484,7 +1484,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),

2
target/riscv/cpu.h
View File

@ -81,6 +81,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVJ RV('J')
#define RVG RV('G')
/* Privileged specification version */
@ -422,7 +423,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
bool ext_g;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;