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linux-user/host/riscv: Improve host_signal_write 

Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-09-17 11:24:14 -07:00
parent 7ce8e389ef
commit 4f3bbd9cfb
1 changed files with 28 additions and 55 deletions
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83
linux-user/host/riscv/host-signal.h
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@ -18,65 +18,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc)
static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
{ {
uint32_t insn = *(uint32_t *)host_signal_pc(uc);
/* /*
* Detect store by reading the instruction at the program * Detect store by reading the instruction at the program counter.
* counter. Note: we currently only generate 32-bit * Do not read more than 16 bits, because we have not yet determined
* instructions so we thus only detect 32-bit stores * the size of the instruction.
*/ */
switch (((insn >> 0) & 0b11)) { const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc);
case 3: uint16_t insn = pinsn[0];
switch (((insn >> 2) & 0b11111)) {
case 8: /* 16-bit instructions */
switch (((insn >> 12) & 0b111)) { switch (insn & 0xe003) {
case 0: /* sb */ case 0xa000: /* c.fsd */
case 1: /* sh */ case 0xc000: /* c.sw */
case 2: /* sw */ case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */
case 3: /* sd */ case 0xa002: /* c.fsdsp */
case 4: /* sq */ case 0xc002: /* c.swsp */
return true; case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */
default: return true;
break;
}
break;
case 9:
switch (((insn >> 12) & 0b111)) {
case 2: /* fsw */
case 3: /* fsd */
case 4: /* fsq */
return true;
default:
break;
}
break;
default:
break;
}
} }
/* Check for compressed instructions */ /* 32-bit instructions, major opcodes */
switch (((insn >> 13) & 0b111)) { switch (insn & 0x7f) {
case 7: case 0x23: /* store */
switch (insn & 0b11) { case 0x27: /* store-fp */
case 0: /*c.sd */ return true;
case 2: /* c.sdsp */ case 0x2f: /* amo */
return true; /*
default: * The AMO function code is in bits 25-31, unread as yet.
break; * The AMO functions are LR (read), SC (write), and the
} * rest are all read-modify-write.
break; */
case 6: insn = pinsn[1];
switch (insn & 0b11) { return (insn >> 11) != 2; /* LR */
case 0: /* c.sw */
case 3: /* c.swsp */
return true;
default:
break;
}
break;
default:
break;
} }
return false; return false;