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target/arm: Extend store_cpu_offset to take field size

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Currently we assume all fields are 32-bit.
Prepare for fields of a single byte, using sizeof_field().

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: use sizeof_field() instead of raw sizeof()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-17 10:43:33 -07:00 committed by Peter Maydell
parent 5322155240
commit 4f4c2a4ba2
2 changed files with 25 additions and 9 deletions
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13
target/arm/translate-a32.h
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@ -61,17 +61,14 @@ static inline TCGv_i32 load_cpu_offset(int offset)
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
static inline void store_cpu_offset(TCGv_i32 var, int offset)
{
tcg_gen_st_i32(var, cpu_env, offset);
tcg_temp_free_i32(var);
}
void store_cpu_offset(TCGv_i32 var, int offset, int size);
#define store_cpu_field(var, name) \
store_cpu_offset(var, offsetof(CPUARMState, name))
#define store_cpu_field(var, name) \
store_cpu_offset(var, offsetof(CPUARMState, name), \
sizeof_field(CPUARMState, name))
#define store_cpu_field_constant(val, name) \
tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, offsetof(CPUARMState, name))
store_cpu_field(tcg_constant_i32(val), name)
/* Create a new temporary and set it to the value of a CPU register. */
static inline TCGv_i32 load_reg(DisasContext *s, int reg)

21
target/arm/translate.c
View File

@ -180,6 +180,25 @@ typedef enum ISSInfo {
ISSIs16Bit = (1 << 8),
} ISSInfo;
/*
* Store var into env + offset to a member with size bytes.
* Free var after use.
*/
void store_cpu_offset(TCGv_i32 var, int offset, int size)
{
switch (size) {
case 1:
tcg_gen_st8_i32(var, cpu_env, offset);
break;
case 4:
tcg_gen_st_i32(var, cpu_env, offset);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_i32(var);
}
/* Save the syndrome information for a Data Abort */
static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo)
{
@ -4852,7 +4871,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_temp_free_i32(tmp);
} else {
TCGv_i32 tmp = load_reg(s, rt);
store_cpu_offset(tmp, ri->fieldoffset);
store_cpu_offset(tmp, ri->fieldoffset, 4);
}
}
}