pull-loongarch-20240125
-----BEGIN PGP SIGNATURE----- iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZbINEAAKCRBAov/yOSY+ 3yVsBACz0E5gVPc5Fp5hgQsAiiZPga/Pr565BOypIw8iAPs0RNxMMnywinFsOi1w A6euynZTEW9lxx5cq/O5j7yaXUmgfChcJ1OkS/IEZaUtiG25ksOIqvoeYvuROfuV nYrM0nuOMNwJzkOJy+qZAwGaUbyWdiqUTkP369V2xxngTneDkw== =1YQg -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20240125' of https://gitlab.com/gaosong/qemu into staging pull-loongarch-20240125 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZbINEAAKCRBAov/yOSY+ # 3yVsBACz0E5gVPc5Fp5hgQsAiiZPga/Pr565BOypIw8iAPs0RNxMMnywinFsOi1w # A6euynZTEW9lxx5cq/O5j7yaXUmgfChcJ1OkS/IEZaUtiG25ksOIqvoeYvuROfuV # nYrM0nuOMNwJzkOJy+qZAwGaUbyWdiqUTkP369V2xxngTneDkw== # =1YQg # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Jan 2024 07:26:08 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240125' of https://gitlab.com/gaosong/qemu: target/loongarch/kvm: Enable LSX/LASX extension target/loongarch: Set cpuid CSR register only once with kvm mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
4f584163c0
@ -79,6 +79,7 @@ struct kvm_fpu {
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#define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT))
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#define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG)
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#define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG)
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#define KVM_LOONGARCH_VCPU_CPUCFG 0
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struct kvm_debug_exit_arch {
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};
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@ -250,7 +250,7 @@ static int kvm_loongarch_get_csr(CPUState *cs)
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return ret;
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}
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static int kvm_loongarch_put_csr(CPUState *cs)
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static int kvm_loongarch_put_csr(CPUState *cs, int level)
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{
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int ret = 0;
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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@ -322,8 +322,11 @@ static int kvm_loongarch_put_csr(CPUState *cs)
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ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG),
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&env->CSR_RVACFG);
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/* CPUID is constant after poweron, it should be set only once */
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if (level >= KVM_PUT_FULL_STATE) {
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ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID),
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&env->CSR_CPUID);
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}
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ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1),
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&env->CSR_PRCFG1);
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@ -537,6 +540,38 @@ static int kvm_loongarch_get_cpucfg(CPUState *cs)
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return ret;
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}
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static int kvm_check_cpucfg2(CPUState *cs)
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{
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int ret;
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uint64_t val;
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struct kvm_device_attr attr = {
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.group = KVM_LOONGARCH_VCPU_CPUCFG,
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.attr = 2,
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.addr = (uint64_t)&val,
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};
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
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if (!ret) {
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kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
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env->cpucfg[2] &= val;
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) {
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/* The FP minimal version is 1. */
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env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, FP_VER, 1);
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}
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LLFTP)) {
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/* The LLFTP minimal version is 1. */
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env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LLFTP_VER, 1);
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}
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}
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return ret;
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}
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static int kvm_loongarch_put_cpucfg(CPUState *cs)
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{
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int i, ret = 0;
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@ -545,14 +580,13 @@ static int kvm_loongarch_put_cpucfg(CPUState *cs)
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uint64_t val;
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for (i = 0; i < 21; i++) {
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val = env->cpucfg[i];
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/* LSX and LASX and LBT are not supported in kvm now */
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if (i == 2) {
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val &= ~(BIT(R_CPUCFG2_LSX_SHIFT) | BIT(R_CPUCFG2_LASX_SHIFT));
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val &= ~(BIT(R_CPUCFG2_LBT_X86_SHIFT) |
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BIT(R_CPUCFG2_LBT_ARM_SHIFT) |
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BIT(R_CPUCFG2_LBT_MIPS_SHIFT));
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ret = kvm_check_cpucfg2(cs);
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if (ret) {
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return ret;
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}
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}
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val = env->cpucfg[i];
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ret = kvm_set_one_reg(cs, KVM_IOC_CPUCFG(i), &val);
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if (ret < 0) {
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trace_kvm_failed_put_cpucfg(strerror(errno));
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@ -598,7 +632,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
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return ret;
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}
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ret = kvm_loongarch_put_csr(cs);
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ret = kvm_loongarch_put_csr(cs, level);
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if (ret) {
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return ret;
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}
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