cpu: Define CPUArchState with typedef
For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
a40ec84ee2
commit
4f7c64b381
@ -26,8 +26,6 @@
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#define ALIGNED_ONLY
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#define CPUArchState struct CPUAlphaState
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/* Alpha processors have a weak memory model */
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#define TCG_GUEST_DEFAULT_MO (0)
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@ -306,6 +304,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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#define cpu_list alpha_cpu_list
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#define cpu_signal_handler cpu_alpha_signal_handler
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typedef CPUAlphaState CPUArchState;
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#include "exec/cpu-all.h"
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enum {
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@ -29,8 +29,6 @@
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/* ARM processors have a weak memory model */
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#define TCG_GUEST_DEFAULT_MO (0)
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#define CPUArchState struct CPUARMState
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_SWI 2 /* software interrupt */
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#define EXCP_PREFETCH_ABORT 3
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@ -3127,6 +3125,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
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}
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}
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typedef CPUARMState CPUArchState;
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#include "exec/cpu-all.h"
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/* Bit usage in the TB flags field: bit 31 indicates whether we are
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@ -25,8 +25,6 @@
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#define CPUArchState struct CPUCRISState
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#define EXCP_NMI 1
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#define EXCP_GURU 2
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#define EXCP_BUSFAULT 3
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@ -286,6 +284,8 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
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#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
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typedef CPUCRISState CPUArchState;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
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@ -31,8 +31,6 @@
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basis. It's probably easier to fall back to a strong memory model. */
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#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
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#define CPUArchState struct CPUHPPAState
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#define ALIGNED_ONLY
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#define MMU_KERNEL_IDX 0
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#define MMU_USER_IDX 3
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@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
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#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e))
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#define ENV_OFFSET offsetof(HPPACPU, env)
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typedef CPUHPPAState CPUArchState;
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#include "exec/cpu-all.h"
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static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
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@ -1,4 +1,3 @@
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/*
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* i386 virtual CPU header
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*
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@ -44,8 +43,6 @@
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#define ELF_MACHINE_UNAME "i686"
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#endif
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#define CPUArchState struct CPUX86State
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enum {
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R_EAX = 0,
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R_ECX = 1,
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@ -1755,6 +1752,8 @@ static inline target_long lshift(target_long x, int n)
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/* translate.c */
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void tcg_x86_init(void);
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typedef CPUX86State CPUArchState;
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#include "exec/cpu-all.h"
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#include "svm.h"
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@ -24,9 +24,6 @@
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#define CPUArchState struct CPULM32State
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struct CPULM32State;
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typedef struct CPULM32State CPULM32State;
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static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
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@ -259,6 +256,8 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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typedef CPULM32State CPUArchState;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
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@ -25,8 +25,6 @@
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#include "exec/cpu-defs.h"
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#include "cpu-qom.h"
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#define CPUArchState struct CPUM68KState
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#define OS_BYTE 0
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#define OS_WORD 1
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#define OS_LONG 2
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@ -538,6 +536,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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typedef CPUM68KState CPUArchState;
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#include "exec/cpu-all.h"
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/* TB flags */
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@ -25,9 +25,6 @@
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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#define CPUArchState struct CPUMBState
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struct CPUMBState;
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typedef struct CPUMBState CPUMBState;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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@ -368,6 +365,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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typedef CPUMBState CPUArchState;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
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@ -3,8 +3,6 @@
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#define ALIGNED_ONLY
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#define CPUArchState struct CPUMIPSState
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#include "qemu-common.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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@ -13,8 +11,6 @@
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#define TCG_GUEST_DEFAULT_MO (0)
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struct CPUMIPSState;
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typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
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/* MSA Context */
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@ -1116,6 +1112,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
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return hflags_mmu_index(env->hflags);
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}
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typedef CPUMIPSState CPUArchState;
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#include "exec/cpu-all.h"
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/*
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@ -23,8 +23,6 @@
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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#define CPUArchState struct CPUMoxieState
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#define MOXIE_EX_DIV0 0
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#define MOXIE_EX_BAD 1
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#define MOXIE_EX_IRQ 2
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@ -119,6 +117,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch)
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return 0;
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}
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typedef CPUMoxieState CPUArchState;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
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@ -25,9 +25,6 @@
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#include "exec/cpu-defs.h"
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#include "qom/cpu.h"
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#define CPUArchState struct CPUNios2State
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struct CPUNios2State;
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typedef struct CPUNios2State CPUNios2State;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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@ -249,6 +246,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State *env)
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return env->regs[CR_STATUS] & CR_STATUS_PIE;
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}
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typedef CPUNios2State CPUArchState;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
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@ -24,8 +24,6 @@
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#include "exec/cpu-defs.h"
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#include "qom/cpu.h"
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#define CPUArchState struct CPUOpenRISCState
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/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
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struct OpenRISCCPU;
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@ -365,6 +363,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
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#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
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typedef CPUOpenRISCState CPUArchState;
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#include "exec/cpu-all.h"
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#define TB_FLAGS_SM SR_SM
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@ -34,8 +34,6 @@
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#define TARGET_PAGE_BITS_64K 16
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#define TARGET_PAGE_BITS_16M 24
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#define CPUArchState struct CPUPPCState
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#if defined(TARGET_PPC64)
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#define PPC_ELF_MACHINE EM_PPC64
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#else
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@ -1377,6 +1375,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
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Error **errp);
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#endif /* defined(TARGET_PPC64) */
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typedef CPUPPCState CPUArchState;
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#include "exec/cpu-all.h"
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/*****************************************************************************/
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@ -27,8 +27,6 @@
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#define TCG_GUEST_DEFAULT_MO 0
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#define CPUArchState struct CPURISCVState
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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@ -336,6 +334,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
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typedef CPURISCVState CPUArchState;
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#include "exec/cpu-all.h"
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#endif /* RISCV_CPU_H */
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@ -28,13 +28,9 @@
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#define ELF_MACHINE_UNAME "S390X"
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#define CPUArchState struct CPUS390XState
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/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
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#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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#include "exec/cpu-all.h"
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#define TARGET_INSN_START_EXTRA_WORDS 1
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#define MMU_MODE0_SUFFIX _primary
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@ -798,4 +794,8 @@ void s390_init_sigp(void);
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/* outside of target/s390x/ */
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S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
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typedef CPUS390XState CPUArchState;
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#include "exec/cpu-all.h"
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#endif
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@ -36,8 +36,6 @@
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#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
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#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
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#define CPUArchState struct CPUSH4State
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#define SR_MD 30
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#define SR_RB 29
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#define SR_BL 28
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@ -282,6 +280,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
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}
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}
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typedef CPUSH4State CPUArchState;
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#include "exec/cpu-all.h"
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/* Memory access type */
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@ -14,8 +14,6 @@
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#define TARGET_DPREGS 32
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#endif
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#define CPUArchState struct CPUSPARCState
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/*#define EXCP_INTERRUPT 0x100*/
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/* trap definitions */
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@ -731,6 +729,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
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#endif
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}
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typedef CPUSPARCState CPUArchState;
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#include "exec/cpu-all.h"
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#ifdef TARGET_SPARC64
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@ -23,8 +23,6 @@
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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#define CPUArchState struct CPUTLGState
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/* TILE-Gx common register alias */
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#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
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#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
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@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
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/* TILE-Gx memory attributes */
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#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
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typedef CPUTLGState CPUArchState;
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#include "exec/cpu-all.h"
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void tilegx_tcg_init(void);
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@ -25,10 +25,6 @@
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#include "exec/cpu-defs.h"
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#include "tricore-defs.h"
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#define CPUArchState struct CPUTriCoreState
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struct CPUTriCoreState;
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struct tricore_boot_info;
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typedef struct tricore_def_t tricore_def_t;
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@ -382,7 +378,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
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return 0;
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}
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typedef CPUTriCoreState CPUArchState;
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#include "exec/cpu-all.h"
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@ -16,8 +16,6 @@
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#define CPUArchState struct CPUUniCore32State
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typedef struct CPUUniCore32State {
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/* Regs for current mode. */
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uint32_t regs[32];
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@ -153,6 +151,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
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return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
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}
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typedef CPUUniCore32State CPUArchState;
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#include "exec/cpu-all.h"
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#define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
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@ -38,8 +38,6 @@
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/* Xtensa processors have a weak memory model */
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#define TCG_GUEST_DEFAULT_MO (0)
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#define CPUArchState struct CPUXtensaState
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enum {
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/* Additional instructions */
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XTENSA_OPTION_CODE_DENSITY,
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@ -801,6 +799,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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}
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}
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typedef CPUXtensaState CPUArchState;
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#include "exec/cpu-all.h"
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#endif
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