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target/xtensa: tests: replace hardcoded interrupt masks

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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2017-01-14 19:58:55 -08:00
parent 72b3b8f24a
commit 4f89b41c28
1 changed files with 5 additions and 5 deletions
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10
tests/tcg/xtensa/test_timer.S
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@ -59,7 +59,7 @@ test ccompare0_interrupt
rsr a2, interrupt rsr a2, interrupt
assert eqi, a2, 0 assert eqi, a2, 0
movi a2, 0x40 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable wsr a2, intenable
rsil a2, 0 rsil a2, 0
loop a3, 1f loop a3, 1f
@ -87,7 +87,7 @@ test ccompare1_interrupt
rsync rsync
rsr a2, interrupt rsr a2, interrupt
assert eqi, a2, 0 assert eqi, a2, 0
movi a2, 0x400 movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable wsr a2, intenable
rsil a2, 2 rsil a2, 2
loop a3, 1f loop a3, 1f
@ -113,7 +113,7 @@ test ccompare2_interrupt
rsync rsync
rsr a2, interrupt rsr a2, interrupt
assert eqi, a2, 0 assert eqi, a2, 0
movi a2, 0x2000 movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable wsr a2, intenable
rsil a2, 4 rsil a2, 4
loop a3, 1f loop a3, 1f
@ -141,7 +141,7 @@ test ccompare_interrupt_masked
rsr a2, interrupt rsr a2, interrupt
assert eqi, a2, 0 assert eqi, a2, 0
movi a2, 0x40 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable wsr a2, intenable
rsil a2, 0 rsil a2, 0
loop a3, 1f loop a3, 1f
@ -171,7 +171,7 @@ test ccompare_interrupt_masked_waiti
rsr a2, interrupt rsr a2, interrupt
assert eqi, a2, 0 assert eqi, a2, 0
movi a2, 0x40 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable wsr a2, intenable
waiti 0 waiti 0
test_fail test_fail