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Softloat updates, mostly in preparation for s390x usage

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-----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAlx1SJ4ACgkQ+9DbCVqe
 KkRLvgf/RyooKgC4+Gien26iuaEEaNJXcPmwPfzC18BiuxIV6GuWAIX3A5X8LRvJ
 HlRj32ervZUMPLk2Amttur9ijh8MCifTt7KyRIFWW1e97WCHX0BuD+DZgD8xT5yX
 zEL8z1MVdyh9ZeBQm930LbcwLeEwtV1jZHCNdlYNhFI4ZlZ8F4SmRdv8rfbAwz0d
 1aC6rDSQhRaY6j5EurTZvDo4s1PA0fYa6LOkWSX/6rCWg1Z2Dtmb16ZTYscBFZ2P
 RhDILojQ6DSPvglcgCYzd/kCQD+OzE3TRSQc40MCS6gX8C4rfAkiuYpDFKNvzdnE
 aAkzemgiBBnslJ0m2VEmfGuJmvXbVg==
 =ApKt
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/stsquad/tags/pull-fpu-next-260219-1' into staging

Softloat updates, mostly in preparation for s390x usage

# gpg: Signature made Tue 26 Feb 2019 14:09:34 GMT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-fpu-next-260219-1:
  tests/Makefile.include: test all rounding modes of softfloat
  softfloat: Support float_round_to_odd more places
  tests/fp: enable f128_to_ui[32/64] tests in float-to-uint
  tests/fp: add wrapping for f128_to_ui32
  softfloat: Implement float128_to_uint32
  softfloat: add float128_is_{normal,denormal}
  tests: Ignore fp test outputs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-02-28 11:13:32 +00:00
commit 4f9ca54d12
6 changed files with 148 additions and 24 deletions
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94
fpu/softfloat.c
View File

@ -696,6 +696,7 @@ static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm,
static FloatParts round_canonical(FloatParts p, float_status *s,
const FloatFmt *parm)
{
const uint64_t frac_lsb = parm->frac_lsb;
const uint64_t frac_lsbm1 = parm->frac_lsbm1;
const uint64_t round_mask = parm->round_mask;
const uint64_t roundeven_mask = parm->roundeven_mask;
@ -731,6 +732,10 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
inc = p.sign ? round_mask : 0;
overflow_norm = !p.sign;
break;
case float_round_to_odd:
overflow_norm = true;
inc = frac & frac_lsb ? 0 : round_mask;
break;
default:
g_assert_not_reached();
}
@ -778,9 +783,14 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
shift64RightJamming(frac, 1 - exp, &frac);
if (frac & round_mask) {
/* Need to recompute round-to-even. */
if (s->float_rounding_mode == float_round_nearest_even) {
switch (s->float_rounding_mode) {
case float_round_nearest_even:
inc = ((frac & roundeven_mask) != frac_lsbm1
? frac_lsbm1 : 0);
break;
case float_round_to_odd:
inc = frac & frac_lsb ? 0 : round_mask;
break;
}
flags |= float_flag_inexact;
frac += inc;
@ -1988,6 +1998,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
case float_round_down:
one = a.sign;
break;
case float_round_to_odd:
one = true;
break;
default:
g_assert_not_reached();
}
@ -2021,6 +2034,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
case float_round_down:
inc = a.sign ? rnd_mask : 0;
break;
case float_round_to_odd:
inc = a.frac & frac_lsb ? 0 : rnd_mask;
break;
default:
g_assert_not_reached();
}
@ -3314,6 +3330,9 @@ static int32_t roundAndPackInt32(flag zSign, uint64_t absZ, float_status *status
case float_round_down:
roundIncrement = zSign ? 0x7f : 0;
break;
case float_round_to_odd:
roundIncrement = absZ & 0x80 ? 0 : 0x7f;
break;
default:
abort();
}
@ -3368,6 +3387,9 @@ static int64_t roundAndPackInt64(flag zSign, uint64_t absZ0, uint64_t absZ1,
case float_round_down:
increment = zSign && absZ1;
break;
case float_round_to_odd:
increment = !(absZ0 & 1) && absZ1;
break;
default:
abort();
}
@ -3424,6 +3446,9 @@ static int64_t roundAndPackUint64(flag zSign, uint64_t absZ0,
case float_round_down:
increment = zSign && absZ1;
break;
case float_round_to_odd:
increment = !(absZ0 & 1) && absZ1;
break;
default:
abort();
}
@ -3526,6 +3551,9 @@ static float32 roundAndPackFloat32(flag zSign, int zExp, uint32_t zSig,
case float_round_down:
roundIncrement = zSign ? 0x7f : 0;
break;
case float_round_to_odd:
roundIncrement = zSig & 0x80 ? 0 : 0x7f;
break;
default:
abort();
break;
@ -3536,8 +3564,10 @@ static float32 roundAndPackFloat32(flag zSign, int zExp, uint32_t zSig,
|| ( ( zExp == 0xFD )
&& ( (int32_t) ( zSig + roundIncrement ) < 0 ) )
) {
bool overflow_to_inf = roundingMode != float_round_to_odd &&
roundIncrement != 0;
float_raise(float_flag_overflow | float_flag_inexact, status);
return packFloat32( zSign, 0xFF, - ( roundIncrement == 0 ));
return packFloat32(zSign, 0xFF, -!overflow_to_inf);
}
if ( zExp < 0 ) {
if (status->flush_to_zero) {
@ -3555,6 +3585,13 @@ static float32 roundAndPackFloat32(flag zSign, int zExp, uint32_t zSig,
if (isTiny && roundBits) {
float_raise(float_flag_underflow, status);
}
if (roundingMode == float_round_to_odd) {
/*
* For round-to-odd case, the roundIncrement depends on
* zSig which just changed.
*/
roundIncrement = zSig & 0x80 ? 0 : 0x7f;
}
}
}
if (roundBits) {
@ -6792,6 +6829,35 @@ uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *status)
return res;
}
/*----------------------------------------------------------------------------
| Returns the result of converting the quadruple-precision floating-point value
| `a' to the 32-bit unsigned integer format. The conversion is
| performed according to the IEC/IEEE Standard for Binary Floating-Point
| Arithmetic---which means in particular that the conversion is rounded
| according to the current rounding mode. If `a' is a NaN, the largest
| positive integer is returned. If the conversion overflows, the
| largest unsigned integer is returned. If 'a' is negative, the value is
| rounded and zero is returned; negative values that do not round to zero
| will raise the inexact exception.
*----------------------------------------------------------------------------*/
uint32_t float128_to_uint32(float128 a, float_status *status)
{
uint64_t v;
uint32_t res;
int old_exc_flags = get_float_exception_flags(status);
v = float128_to_uint64(a, status);
if (v > 0xffffffff) {
res = 0xffffffff;
} else {
return v;
}
set_float_exception_flags(old_exc_flags, status);
float_raise(float_flag_invalid, status);
return res;
}
/*----------------------------------------------------------------------------
| Returns the result of converting the quadruple-precision floating-point
| value `a' to the single-precision floating-point format. The conversion
@ -6958,6 +7024,15 @@ float128 float128_round_to_int(float128 a, float_status *status)
add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low);
}
break;
case float_round_to_odd:
/*
* Note that if lastBitMask == 0, the last bit is the lsb
* of high, and roundBitsMask == -1.
*/
if ((lastBitMask ? z.low & lastBitMask : z.high & 1) == 0) {
add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low);
}
break;
default:
abort();
}
@ -6969,7 +7044,7 @@ float128 float128_round_to_int(float128 a, float_status *status)
status->float_exception_flags |= float_flag_inexact;
aSign = extractFloat128Sign( a );
switch (status->float_rounding_mode) {
case float_round_nearest_even:
case float_round_nearest_even:
if ( ( aExp == 0x3FFE )
&& ( extractFloat128Frac0( a )
| extractFloat128Frac1( a ) )
@ -6982,14 +7057,17 @@ float128 float128_round_to_int(float128 a, float_status *status)
return packFloat128(aSign, 0x3FFF, 0, 0);
}
break;
case float_round_down:
case float_round_down:
return
aSign ? packFloat128( 1, 0x3FFF, 0, 0 )
: packFloat128( 0, 0, 0, 0 );
case float_round_up:
case float_round_up:
return
aSign ? packFloat128( 1, 0, 0, 0 )
: packFloat128( 0, 0x3FFF, 0, 0 );
case float_round_to_odd:
return packFloat128(aSign, 0x3FFF, 0, 0);
}
return packFloat128( aSign, 0, 0, 0 );
}
@ -7022,6 +7100,12 @@ float128 float128_round_to_int(float128 a, float_status *status)
z.high += roundBitsMask;
}
break;
case float_round_to_odd:
if ((z.high & lastBitMask) == 0) {
z.high |= (a.low != 0);
z.high += roundBitsMask;
}
break;
default:
abort();
}

15
include/fpu/softfloat.h
View File

@ -466,7 +466,7 @@ static inline int float32_is_zero_or_denormal(float32 a)
static inline bool float32_is_normal(float32 a)
{
return ((float32_val(a) + 0x00800000) & 0x7fffffff) >= 0x01000000;
return (((float32_val(a) >> 23) + 1) & 0xff) >= 2;
}
static inline bool float32_is_denormal(float32 a)
@ -622,7 +622,7 @@ static inline int float64_is_zero_or_denormal(float64 a)
static inline bool float64_is_normal(float64 a)
{
return ((float64_val(a) + (1ULL << 52)) & -1ULL >> 1) >= 1ULL << 53;
return (((float64_val(a) >> 52) + 1) & 0x7ff) >= 2;
}
static inline bool float64_is_denormal(float64 a)
@ -878,6 +878,7 @@ int64_t float128_to_int64(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
uint32_t float128_to_uint32(float128, float_status *status);
uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
float64 float128_to_float64(float128, float_status *status);
@ -940,6 +941,16 @@ static inline int float128_is_zero_or_denormal(float128 a)
return (a.high & 0x7fff000000000000LL) == 0;
}
static inline bool float128_is_normal(float128 a)
{
return (((a.high >> 48) + 1) & 0x7fff) >= 2;
}
static inline bool float128_is_denormal(float128 a)
{
return float128_is_zero_or_denormal(a) && !float128_is_zero(a);
}
static inline int float128_is_any_nan(float128 a)
{
return ((a.high >> 48) & 0x7fff) == 0x7fff &&

1
tests/.gitignore vendored
View File

@ -5,6 +5,7 @@ benchmark-crypto-hmac
check-*
!check-*.c
!check-*.sh
fp/*.out
qht-bench
rcutorture
test-*

15
tests/Makefile.include
View File

@ -916,19 +916,18 @@ $(FP_TEST_BIN):
# The full test suite can take a bit of time, default to a quick run
# "-l 2 -r all" can take more than a day for some operations and is best
# run manually
FP_TL=-l 1
FP_TL=-l 1 -r all
# $1 = tests, $2 = description
# $1 = tests, $2 = description, $3 = test flags
test-softfloat = $(call quiet-command, \
cd $(BUILD_DIR)/tests/fp && \
./fp-test -s $(FP_TL) $1 > $2.out 2>&1 || \
./fp-test -s $(if $3,$3,$(FP_TL)) $1 > $2.out 2>&1 || \
(cat $2.out && exit 1;), \
"FLOAT TEST", $2)
# Conversion Routines:
# FIXME: i32_to_extF80 (broken), i64_to_extF80 (broken)
# ui32_to_f128 (not implemented), f128_to_ui32 (not implemented)
# extF80_roundToInt (broken)
# ui32_to_f128 (not implemented), extF80_roundToInt (broken)
#
check-softfloat-conv: $(FP_TEST_BIN)
$(call test-softfloat, \
@ -957,9 +956,11 @@ check-softfloat-conv: $(FP_TEST_BIN)
f16_to_ui32 f16_to_ui32_r_minMag \
f32_to_ui32 f32_to_ui32_r_minMag \
f64_to_ui32 f64_to_ui32_r_minMag \
f128_to_ui32 f128_to_ui32_r_minMag \
f16_to_ui64 f16_to_ui64_r_minMag \
f32_to_ui64 f32_to_ui64_r_minMag \
f64_to_ui64 f64_to_ui64_r_minMag, \
f64_to_ui64 f64_to_ui64_r_minMag \
f128_to_ui64 f128_to_ui64_r_minMag, \
float-to-uint)
$(call test-softfloat, \
f16_roundToInt f32_roundToInt \
@ -1001,7 +1002,7 @@ check-softfloat-compare: $(SF_COMPARE_RULES)
check-softfloat-mulAdd: $(FP_TEST_BIN)
$(call test-softfloat, \
f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd, \
mulAdd)
mulAdd,-l 1)
# FIXME: extF80_rem (broken)
check-softfloat-rem: $(FP_TEST_BIN)

46
tests/fp/fp-test.c
View File

@ -125,17 +125,42 @@ static void not_implemented(void)
static bool blacklisted(unsigned op, int rmode)
{
/* odd has only been implemented for a few 128-bit ops */
/* odd has not been implemented for any 80-bit ops */
if (rmode == softfloat_round_odd) {
switch (op) {
case F128_ADD:
case F128_SUB:
case F128_MUL:
case F128_DIV:
case F128_TO_F64:
case F128_SQRT:
return false;
default:
case EXTF80_TO_UI32:
case EXTF80_TO_UI64:
case EXTF80_TO_I32:
case EXTF80_TO_I64:
case EXTF80_TO_UI32_R_MINMAG:
case EXTF80_TO_UI64_R_MINMAG:
case EXTF80_TO_I32_R_MINMAG:
case EXTF80_TO_I64_R_MINMAG:
case EXTF80_TO_F16:
case EXTF80_TO_F32:
case EXTF80_TO_F64:
case EXTF80_TO_F128:
case EXTF80_ROUNDTOINT:
case EXTF80_ADD:
case EXTF80_SUB:
case EXTF80_MUL:
case EXTF80_DIV:
case EXTF80_REM:
case EXTF80_SQRT:
case EXTF80_EQ:
case EXTF80_LE:
case EXTF80_LT:
case EXTF80_EQ_SIGNALING:
case EXTF80_LE_QUIET:
case EXTF80_LT_QUIET:
case UI32_TO_EXTF80:
case UI64_TO_EXTF80:
case I32_TO_EXTF80:
case I64_TO_EXTF80:
case F16_TO_EXTF80:
case F32_TO_EXTF80:
case F64_TO_EXTF80:
case F128_TO_EXTF80:
return true;
}
}
@ -622,7 +647,8 @@ static void do_testfloat(int op, int rmode, bool exact)
test_ab_extF80_z_bool(true_ab_extF80M_z_bool, subj_ab_extF80M_z_bool);
break;
case F128_TO_UI32:
not_implemented();
test_a_f128_z_ui32_rx(slow_f128M_to_ui32, qemu_f128M_to_ui32, rmode,
exact);
break;
case F128_TO_UI64:
test_a_f128_z_ui64_rx(slow_f128M_to_ui64, qemu_f128M_to_ui64, rmode,

1
tests/fp/wrap.inc.c
View File

@ -367,6 +367,7 @@ WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag,
WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t)
WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t)
WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t)
WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t)
#undef WRAP_128_TO_INT