Emulate address wrap in CFI02 chips mapping (Jan Kiszka).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4219 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
6725070d8d
commit
4fbd24ba35
@ -11,7 +11,7 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
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/* pflash_cfi02.c */
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pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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BlockDriverState *bs, uint32_t sector_len,
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int nb_blocs, int width,
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int nb_blocs, int nb_mappings, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0, uint16_t unlock_addr1);
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@ -55,7 +55,8 @@ struct pflash_t {
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BlockDriverState *bs;
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target_phys_addr_t base;
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uint32_t sector_len;
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uint32_t total_len;
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uint32_t chip_len;
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int mappings;
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int width;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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@ -72,6 +73,19 @@ struct pflash_t {
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void *storage;
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};
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static void pflash_register_memory(pflash_t *pfl, int rom_mode)
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{
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unsigned long phys_offset = pfl->fl_mem;
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int i;
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if (rom_mode)
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phys_offset |= pfl->off | IO_MEM_ROMD;
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for (i = 0; i < pfl->mappings; i++)
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cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
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pfl->chip_len, phys_offset);
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}
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static void pflash_timer (void *opaque)
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{
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pflash_t *pfl = opaque;
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@ -82,8 +96,7 @@ static void pflash_timer (void *opaque)
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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cpu_register_physical_memory(pfl->base, pfl->total_len,
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pfl->off | IO_MEM_ROMD | pfl->fl_mem);
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pflash_register_memory(pfl, 1);
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pfl->wcycle = 0;
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}
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pfl->cmd = 0;
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@ -98,6 +111,7 @@ static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
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DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
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ret = -1;
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offset -= pfl->base;
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2)
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boff = boff >> 1;
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@ -226,11 +240,10 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
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offset -= (uint32_t)(long)pfl->storage;
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else
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offset -= pfl->base;
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offset &= pfl->chip_len - 1;
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
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offset, value, width);
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/* Set the device in I/O access mode */
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cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2)
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boff = boff >> 1;
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@ -238,6 +251,8 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
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boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0:
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/* Set the device in I/O access mode */
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pflash_register_memory(pfl, 0);
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/* We're in read mode */
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check_unlock0:
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if (boff == 0x55 && cmd == 0x98) {
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@ -369,9 +384,9 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
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}
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/* Chip erase */
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DPRINTF("%s: start chip erase\n", __func__);
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memset(pfl->storage, 0xFF, pfl->total_len);
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memset(pfl->storage, 0xFF, pfl->chip_len);
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pfl->status = 0x00;
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pflash_update(pfl, 0, pfl->total_len);
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pflash_update(pfl, 0, pfl->chip_len);
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/* Let's wait 5 seconds before chip erase is done */
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qemu_mod_timer(pfl->timer,
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qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
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@ -424,8 +439,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
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/* Reset flash */
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reset_flash:
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cpu_register_physical_memory(pfl->base, pfl->total_len,
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pfl->off | IO_MEM_ROMD | pfl->fl_mem);
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pflash_register_memory(pfl, 1);
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pfl->bypass = 0;
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pfl->wcycle = 0;
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pfl->cmd = 0;
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@ -527,15 +541,15 @@ static int ctz32 (uint32_t n)
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pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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BlockDriverState *bs, uint32_t sector_len,
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int nb_blocs, int width,
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int nb_blocs, int nb_mappings, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0, uint16_t unlock_addr1)
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{
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pflash_t *pfl;
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int32_t total_len;
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int32_t chip_len;
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total_len = sector_len * nb_blocs;
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chip_len = sector_len * nb_blocs;
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/* XXX: to be fixed */
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#if 0
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if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
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@ -549,12 +563,14 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
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pfl);
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pfl->off = off;
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cpu_register_physical_memory(base, total_len,
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off | pfl->fl_mem | IO_MEM_ROMD);
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pfl->base = base;
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pfl->chip_len = chip_len;
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pfl->mappings = nb_mappings;
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pflash_register_memory(pfl, 1);
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pfl->bs = bs;
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if (pfl->bs) {
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/* read the initial flash content */
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bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
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bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
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}
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#if 0 /* XXX: there should be a bit to set up read-only,
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* the same way the hardware does (with WP pin).
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@ -564,9 +580,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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pfl->ro = 0;
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#endif
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pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
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pfl->base = base;
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pfl->sector_len = sector_len;
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pfl->total_len = total_len;
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pfl->width = width;
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pfl->wcycle = 0;
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pfl->cmd = 0;
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@ -620,7 +634,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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/* Max timeout for chip erase */
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pfl->cfi_table[0x26] = 0x0D;
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/* Device size */
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pfl->cfi_table[0x27] = ctz32(total_len) + 1;
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pfl->cfi_table[0x27] = ctz32(chip_len) + 1;
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/* Flash device interface (8 & 16 bits) */
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pfl->cfi_table[0x28] = 0x02;
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pfl->cfi_table[0x29] = 0x00;
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@ -235,8 +235,8 @@ static void ref405ep_init (int ram_size, int vga_ram_size,
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bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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drives_table[index].bdrv, 65536, fl_sectors, 2,
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0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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drives_table[index].bdrv, 65536, fl_sectors, 1,
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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fl_idx++;
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} else
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#endif
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@ -552,8 +552,8 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size,
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bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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drives_table[index].bdrv, 65536, fl_sectors, 4,
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0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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drives_table[index].bdrv, 65536, fl_sectors, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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fl_idx++;
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} else
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#endif
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@ -588,8 +588,8 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size,
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bdrv_get_device_name(drives_table[index].bdrv));
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#endif
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pflash_cfi02_register(0xfc000000, bios_offset,
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drives_table[index].bdrv, 65536, fl_sectors, 4,
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0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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drives_table[index].bdrv, 65536, fl_sectors, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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fl_idx++;
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}
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/* Register CLPD & LCD display */
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