target/ppc: Rewrite trans_ADDG6S
Compute all carry bits in parallel instead of a loop. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
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static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
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{
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const uint64_t carry_bits = 0x1111111111111111ULL;
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TCGv t0, t1, carry, zero = tcg_constant_tl(0);
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const target_ulong carry_bits = (target_ulong)-1 / 0xf;
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TCGv in1, in2, carryl, carryh, tmp;
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TCGv zero = tcg_constant_tl(0);
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REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
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t0 = tcg_temp_new();
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t1 = tcg_const_tl(0);
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carry = tcg_const_tl(0);
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in1 = cpu_gpr[a->ra];
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in2 = cpu_gpr[a->rb];
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tmp = tcg_temp_new();
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carryl = tcg_temp_new();
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carryh = tcg_temp_new();
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for (int i = 0; i < 16; i++) {
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tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
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tcg_gen_andi_tl(t0, t0, 0xf);
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tcg_gen_add_tl(t1, t1, t0);
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/* Addition with carry. */
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tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
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/* Addition without carry. */
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tcg_gen_xor_tl(tmp, in1, in2);
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/* Difference between the two is carry in to each bit. */
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tcg_gen_xor_tl(carryl, carryl, tmp);
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tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
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tcg_gen_andi_tl(t0, t0, 0xf);
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tcg_gen_add_tl(t1, t1, t0);
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/*
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* The carry-out that we're looking for is the carry-in to
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* the next nibble. Shift the double-word down one nibble,
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* which puts all of the bits back into one word.
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*/
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tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
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tcg_gen_andi_tl(t1, t1, 0x10);
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tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
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tcg_gen_shli_tl(t0, t1, i * 4);
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tcg_gen_or_tl(carry, carry, t0);
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}
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tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
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tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
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/* Invert, isolate the carry bits, and produce 6's. */
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tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
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tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
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return true;
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}
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