QOM CPUState refactorings
* Fix x86 cpu-add * Change KVM PMU behavior for 1.6 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAABAgAGBQJR9ooSAAoJEPou0S0+fgE/+04QALXCQnbPGqIJNyAstf8TnOlH UzyyLzwnTpifwBDxk97PcCjpWKIoMozqMfyChKycTCvn2DIEKNV9QIGydmp1RXJF ILQGX3J8iBPDFGoGWGG41dPJPr1ELwA5An5OylrGnqoGq0u6tIv82Lr+UkDMSq24 IgUo+dJbJ33qWH2dwB6ctcEZPtqfCseuGBmOoJNHiuYMHvH+G6Rcg+zAP5n8gFTV 7cKDZ6xCZrAlZVADPUy2XO3PO7kDY3UTUWGvA2MqTjk7u1Hm5hOnY30QZrz4FVTm huR+AsDX0B6q5sSDKiZUSPHe0f1f7keGf4/YXOtVTHhANjoMg4NiJp4KMdVjZYmQ 2zZRudktDEZ8eYmHIqCQ08ZH53D2zkpQ3fvr4hoTS5uDjH6x6pqKvQlcC5RbCDsn YZVxeD/NM/aRJb2N4Q4ihnNWMbHMZW6NMijYS7nk+SlU6iGb/7DR3YRgmKvfevtE WQVt26n+m+6avPGq+RIJZ9DxrYuESmz1qYFMjbH5deN8kdsHoLQfM1q7y8SJmTeI gXT1GVg25qzsmPa7t7nUWWleqn6kBoe9pHhb6xiIG5TNzXQyA+cPEqngxXDRYmxx HmSjWoRr0uMN3jVJqDXl9qjayDDGuZ7tiA4iOzhzw34yY3iNGU2QWNXM01ZFsd+5 06MySKkf6PE94OxFiYo3 =7lWx -----END PGP SIGNATURE----- Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging QOM CPUState refactorings * Fix x86 cpu-add * Change KVM PMU behavior for 1.6 # gpg: Signature made Mon 29 Jul 2013 10:28:18 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Eduardo Habkost (2) and Andreas Färber (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Disable PMU CPUID leaf by default target-i386: Pass X86CPU object to cpu_x86_find_by_name() cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
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commit
4ff1fac430
@ -235,6 +235,10 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
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.driver = "virtio-net-pci",\
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.property = "any_layout",\
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.value = "off",\
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},{\
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.driver = TYPE_X86_CPU,\
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.property = "pmu",\
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.value = "on",\
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}
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#define PC_COMPAT_1_4 \
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@ -228,8 +228,6 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cpu = CPU(dev);
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qemu_init_vcpu(cpu);
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if (dev->hotplugged) {
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cpu_synchronize_post_init(cpu);
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notifier_list_notify(&cpu_added_notifiers, dev);
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@ -33,8 +33,11 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
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static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
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qemu_init_vcpu(cs);
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acc->parent_realize(dev, errp);
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}
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@ -159,6 +159,7 @@ static void arm_cpu_finalizefn(Object *obj)
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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ARMCPU *cpu = ARM_CPU(dev);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
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CPUARMState *env = &cpu->env;
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@ -214,7 +215,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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init_cpreg_list(cpu);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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acc->parent_realize(dev, errp);
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}
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@ -137,10 +137,11 @@ void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CRISCPU *cpu = CRIS_CPU(dev);
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CPUState *cs = CPU(dev);
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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ccc->parent_realize(dev, errp);
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}
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@ -68,6 +68,13 @@ typedef struct X86CPU {
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/* Features that were filtered out because of missing host capabilities */
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uint32_t filtered_features[FEATURE_WORDS];
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/* Enable PMU CPUID bits. This can't be enabled by default yet because
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* it doesn't have ABI stability guarantees, as it passes all PMU CPUID
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* bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
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* capabilities) directly to the guest.
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*/
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bool enable_pmu;
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} X86CPU;
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static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
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@ -1475,9 +1475,11 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
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error_propagate(errp, err);
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}
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static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
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static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
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const char *name)
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{
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x86_def_t *def;
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Error *err = NULL;
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int i;
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if (name == NULL) {
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@ -1485,6 +1487,8 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
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}
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if (kvm_enabled() && strcmp(name, "host") == 0) {
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kvm_cpu_fill_host(x86_cpu_def);
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object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
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assert_no_error(err);
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return 0;
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}
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@ -1742,7 +1746,7 @@ static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
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memset(def, 0, sizeof(*def));
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if (cpu_x86_find_by_name(def, name) < 0) {
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if (cpu_x86_find_by_name(cpu, def, name) < 0) {
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error_setg(errp, "Unable to find CPU definition: %s", name);
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return;
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}
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@ -2016,7 +2020,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0xA:
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/* Architectural Performance Monitoring Leaf */
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if (kvm_enabled()) {
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if (kvm_enabled() && cpu->enable_pmu) {
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KVMState *s = cs->kvm_state;
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*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
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@ -2333,6 +2337,7 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
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static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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X86CPU *cpu = X86_CPU(dev);
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X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
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CPUX86State *env = &cpu->env;
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@ -2387,12 +2392,13 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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#endif
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mce_init(cpu);
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qemu_init_vcpu(cs);
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x86_cpu_apic_realize(cpu, &local_err);
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if (local_err != NULL) {
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goto out;
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}
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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xcc->parent_realize(dev, &local_err);
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out:
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@ -2520,6 +2526,11 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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cpu->env.eip = tb->pc - tb->cs_base;
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}
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static Property x86_cpu_properties[] = {
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DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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{
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X86CPUClass *xcc = X86_CPU_CLASS(oc);
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@ -2529,6 +2540,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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xcc->parent_realize = dc->realize;
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dc->realize = x86_cpu_realizefn;
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dc->bus_type = TYPE_ICC_BUS;
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dc->props = x86_cpu_properties;
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xcc->parent_reset = cc->reset;
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cc->reset = x86_cpu_reset;
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@ -46,10 +46,12 @@ static void lm32_cpu_reset(CPUState *s)
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static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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LM32CPU *cpu = LM32_CPU(dev);
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CPUState *cs = CPU(dev);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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lcc->parent_realize(dev, errp);
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}
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@ -143,12 +143,14 @@ static const M68kCPUInfo m68k_cpus[] = {
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static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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M68kCPU *cpu = M68K_CPU(dev);
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M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
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m68k_cpu_init_gdb(cpu);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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@ -90,10 +90,11 @@ static void mb_cpu_reset(CPUState *s)
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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@ -62,10 +62,11 @@ static void mips_cpu_reset(CPUState *s)
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static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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MIPSCPU *cpu = MIPS_CPU(dev);
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CPUState *cs = CPU(dev);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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@ -45,10 +45,11 @@ static void moxie_cpu_reset(CPUState *s)
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static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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MoxieCPU *cpu = MOXIE_CPU(dev);
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CPUState *cs = CPU(dev);
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MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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mcc->parent_realize(dev, errp);
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}
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@ -66,10 +66,11 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature)
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static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(dev);
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CPUState *cs = CPU(dev);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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occ->parent_realize(dev, errp);
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}
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@ -7861,6 +7861,8 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
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34, "power-spe.xml", 0);
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}
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qemu_init_vcpu(cs);
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pcc->parent_realize(dev, errp);
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#if defined(PPC_DUMP_CPU)
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@ -101,10 +101,11 @@ static void s390_cpu_machine_reset_cb(void *opaque)
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static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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S390CPU *cpu = S390_CPU(dev);
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CPUState *cs = CPU(dev);
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S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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scc->parent_realize(dev, errp);
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}
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@ -240,10 +240,11 @@ static const TypeInfo sh7785_type_info = {
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static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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SuperHCPU *cpu = SUPERH_CPU(dev);
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CPUState *cs = CPU(dev);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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scc->parent_realize(dev, errp);
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}
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@ -743,6 +743,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
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qemu_init_vcpu(CPU(dev));
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scc->parent_realize(dev, errp);
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}
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@ -92,6 +92,8 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
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qemu_init_vcpu(CPU(dev));
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ucc->parent_realize(dev, errp);
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}
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@ -90,6 +90,8 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
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qemu_init_vcpu(cs);
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xcc->parent_realize(dev, errp);
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}
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