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cadence_gem: Don't reset rx desc pointer on rx_en 

This doesn't happen in the real hardware. The Zynq TRM explicitly states that
this bit has no effect on the rx descriptor pointer ("The receive queue
pointer register is unaffected").

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 06fdf92b78ee62d8965779bafd29c8df1a5d2718.1360901435.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite 2013-02-28 18:23:16 +00:00 committed by Peter Maydell
parent ae80a3546f
commit 5025388b50
1 changed files with 0 additions and 4 deletions
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4
hw/cadence_gem.c
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@ -1083,10 +1083,6 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
/* Reset to start of Q when transmit disabled. */
s->tx_desc_addr = s->regs[GEM_TXQBASE];
}
if (!(val & GEM_NWCTRL_RXENA)) {
/* Reset to start of Q when receive disabled. */
s->rx_desc_addr = s->regs[GEM_RXQBASE];
}
if (val & GEM_NWCTRL_RXENA) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}