OpenE2K/qemu-e2k
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msix: track function masked in pci device state

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Only go over the table when function is masked.
This is not really important for qemu.git but helps
fix a bug in qemu-kvm.git.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Michael S. Tsirkin 2011-11-21 18:57:21 +02:00 committed by Anthony Liguori
parent 2923d34fdc
commit 50322249fd
2 changed files with 16 additions and 7 deletions
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21
hw/msix.c
View File

@ -79,6 +79,7 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
/* Make flags bit writable. */ /* Make flags bit writable. */
pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK; MSIX_MASKALL_MASK;
pdev->msix_function_masked = true;
return 0; return 0;
} }
@ -117,16 +118,11 @@ static void msix_clr_pending(PCIDevice *dev, int vector)
*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
} }
static int msix_function_masked(PCIDevice *dev)
{
return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
}
static int msix_is_masked(PCIDevice *dev, int vector) static int msix_is_masked(PCIDevice *dev, int vector)
{ {
unsigned offset = unsigned offset =
vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
return msix_function_masked(dev) || return dev->msix_function_masked ||
dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT; dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
} }
@ -138,24 +134,34 @@ static void msix_handle_mask_update(PCIDevice *dev, int vector)
} }
} }
static void msix_update_function_masked(PCIDevice *dev)
{
dev->msix_function_masked = !msix_enabled(dev) ||
(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
}
/* Handle MSI-X capability config write. */ /* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr, void msix_write_config(PCIDevice *dev, uint32_t addr,
uint32_t val, int len) uint32_t val, int len)
{ {
unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET; unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
int vector; int vector;
bool was_masked;
if (!range_covers_byte(addr, len, enable_pos)) { if (!range_covers_byte(addr, len, enable_pos)) {
return; return;
} }
was_masked = dev->msix_function_masked;
msix_update_function_masked(dev);
if (!msix_enabled(dev)) { if (!msix_enabled(dev)) {
return; return;
} }
pci_device_deassert_intx(dev); pci_device_deassert_intx(dev);
if (msix_function_masked(dev)) { if (dev->msix_function_masked == was_masked) {
return; return;
} }
@ -300,6 +306,7 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
msix_free_irq_entries(dev); msix_free_irq_entries(dev);
qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
msix_update_function_masked(dev);
} }
/* Does device support MSI-X? */ /* Does device support MSI-X? */

2
hw/pci.h
View File

@ -178,6 +178,8 @@ struct PCIDevice {
unsigned *msix_entry_used; unsigned *msix_entry_used;
/* Region including the MSI-X table */ /* Region including the MSI-X table */
uint32_t msix_bar_size; uint32_t msix_bar_size;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */ /* Version id needed for VMState */
int32_t version_id; int32_t version_id;