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target/ppc: Implement Vector Compare Greater Than Quadword

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Implement the following PowerISA v3.1 instructions:
vcmpgtsq: Vector Compare Greater Than Signed Quadword
vcmpgtuq: Vector Compare Greater Than Unsigned Quadword

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-13-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 committed by Cédric Le Goater
parent 7b3da08e3c
commit 50449ae482
2 changed files with 41 additions and 0 deletions
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2
target/ppc/insn32.decode
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@ -388,11 +388,13 @@ VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
VCMPGTSQ 000100 ..... ..... ..... . 1110000111 @VC
VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
VCMPGTUQ 000100 ..... ..... ..... . 1010000111 @VC
VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC

39
target/ppc/translate/vmx-impl.c.inc
View File

@ -1143,6 +1143,45 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
return true;
}
static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
{
TCGv_i64 t0, t1, t2;
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
get_avr64(t0, a->vra, false);
get_avr64(t1, a->vrb, false);
tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
get_avr64(t0, a->vra, true);
get_avr64(t1, a->vrb, true);
tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_neg_i64(t1, t1);
set_avr64(a->vrt, t1, true);
set_avr64(a->vrt, t1, false);
if (a->rc) {
tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return true;
}
TRANS(VCMPGTSQ, do_vcmpgtq, true)
TRANS(VCMPGTUQ, do_vcmpgtq, false)
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)