target-alpha: Merge HW_REI and HW_RET implementations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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8417845ee9
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508b43eaf3
@ -100,7 +100,6 @@ DEF_HELPER_1(ieee_input_cmp, i64, i64)
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DEF_HELPER_1(ieee_input_s, i64, i64)
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#if !defined (CONFIG_USER_ONLY)
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DEF_HELPER_0(hw_rei, void)
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DEF_HELPER_1(hw_ret, void, i64)
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DEF_HELPER_2(mfpr, i64, int, i64)
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DEF_HELPER_2(mtpr, void, int, i64)
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@ -1156,22 +1156,12 @@ uint64_t helper_cvtqg (uint64_t a)
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/* PALcode support special instructions */
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#if !defined (CONFIG_USER_ONLY)
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void helper_hw_rei (void)
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{
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env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
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env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
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env->intr_flag = 0;
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env->lock_addr = -1;
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/* XXX: re-enable interrupts and memory mapping */
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}
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void helper_hw_ret (uint64_t a)
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{
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env->pc = a & ~3;
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env->ipr[IPR_EXC_ADDR] = a & 1;
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env->intr_flag = 0;
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env->lock_addr = -1;
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/* XXX: re-enable interrupts and memory mapping */
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}
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uint64_t helper_mfpr (int iprn, uint64_t val)
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@ -2876,25 +2876,22 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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#endif
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case 0x1E:
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/* HW_REI (PALcode) */
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/* HW_RET (PALcode) */
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#if defined (CONFIG_USER_ONLY)
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goto invalid_opc;
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#else
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if (!ctx->pal_mode)
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goto invalid_opc;
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if (rb == 31) {
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/* "Old" alpha */
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gen_helper_hw_rei();
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} else {
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TCGv tmp;
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if (ra != 31) {
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tmp = tcg_temp_new();
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tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
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} else
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tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
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/* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
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address from EXC_ADDR. This turns out to be useful for our
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emulation PALcode, so continue to accept it. */
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TCGv tmp = tcg_temp_new();
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tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, ipr[IPR_EXC_ADDR]));
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gen_helper_hw_ret(tmp);
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tcg_temp_free(tmp);
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} else {
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gen_helper_hw_ret(cpu_ir[rb]);
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}
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ret = EXIT_PC_UPDATED;
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break;
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