target/arm: Reuse sve_probe_page for gather first-fault loads
This avoids the need for a separate set of helpers to implement no-fault semantics, and will enable MTE in the future. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
0fa476c1bb
commit
50de9b78ce
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@ -5254,231 +5254,162 @@ DO_LD1_ZPZ_D(dd_be, zd)
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/* First fault loads with a vector index. */
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/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
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* The controlling predicate is known to be true. Return true if the
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* load was successful.
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*/
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typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
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target_ulong vaddr, int mmu_idx);
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#ifdef CONFIG_SOFTMMU
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#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
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static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
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target_ulong addr, int mmu_idx) \
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{ \
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target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
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if (likely(next_page - addr >= sizeof(TYPEM))) { \
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void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
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if (likely(host)) { \
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TYPEM val = HOST(host); \
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*(TYPEE *)(vd + H(reg_off)) = val; \
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return true; \
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} \
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} \
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return false; \
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}
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#else
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#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
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static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
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target_ulong addr, int mmu_idx) \
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{ \
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if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
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TYPEM val = HOST(g2h(addr)); \
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*(TYPEE *)(vd + H(reg_off)) = val; \
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return true; \
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} \
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return false; \
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}
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#endif
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DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
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DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
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DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
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DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
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DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
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DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
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DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
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DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
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DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
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DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
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DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
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DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
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DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
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DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
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DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
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DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
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DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
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DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
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DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
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DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
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/*
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* Common helper for all gather first-faulting loads.
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* Common helpers for all gather first-faulting loads.
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*/
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static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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target_ulong base, uint32_t desc, uintptr_t ra,
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zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
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sve_ld1_nf_fn *nonfault_fn)
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static inline QEMU_ALWAYS_INLINE
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void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
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target_ulong base, uint32_t desc, uintptr_t retaddr,
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const int esz, const int msz, zreg_off_fn *off_fn,
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sve_ldst1_host_fn *host_fn,
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sve_ldst1_tlb_fn *tlb_fn)
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{
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const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
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const int mmu_idx = get_mmuidx(oi);
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const int mmu_idx = cpu_mmu_index(env, false);
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const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
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intptr_t reg_off, reg_max = simd_oprsz(desc);
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target_ulong addr;
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const int esize = 1 << esz;
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const int msize = 1 << msz;
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const intptr_t reg_max = simd_oprsz(desc);
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intptr_t reg_off;
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SVEHostPage info;
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target_ulong addr, in_page;
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/* Skip to the first true predicate. */
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reg_off = find_next_active(vg, 0, reg_max, MO_32);
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if (likely(reg_off < reg_max)) {
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/* Perform one normal read, which will fault or not. */
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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tlb_fn(env, vd, reg_off, addr, ra);
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/* The rest of the reads will be non-faulting. */
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reg_off = find_next_active(vg, 0, reg_max, esz);
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if (unlikely(reg_off >= reg_max)) {
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/* The entire predicate was false; no load occurs. */
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memset(vd, 0, reg_max);
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return;
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}
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/* After any fault, zero the leading predicated false elements. */
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/*
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* Probe the first element, allowing faults.
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*/
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addr = base + (off_fn(vm, reg_off) << scale);
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tlb_fn(env, vd, reg_off, addr, retaddr);
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/* After any fault, zero the other elements. */
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swap_memzero(vd, reg_off);
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reg_off += esize;
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swap_memzero(vd + reg_off, reg_max - reg_off);
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while (likely((reg_off += 4) < reg_max)) {
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uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
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if (likely((pg >> (reg_off & 63)) & 1)) {
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
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record_fault(env, reg_off, reg_max);
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break;
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/*
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* Probe the remaining elements, not allowing faults.
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*/
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while (reg_off < reg_max) {
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uint64_t pg = vg[reg_off >> 6];
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do {
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if (likely((pg >> (reg_off & 63)) & 1)) {
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addr = base + (off_fn(vm, reg_off) << scale);
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in_page = -(addr | TARGET_PAGE_MASK);
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if (unlikely(in_page < msize)) {
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/* Stop if the element crosses a page boundary. */
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goto fault;
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}
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sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
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mmu_idx, retaddr);
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if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
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goto fault;
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}
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if (unlikely(info.flags & TLB_WATCHPOINT) &&
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(cpu_watchpoint_address_matches
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(env_cpu(env), addr, msize) & BP_MEM_READ)) {
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goto fault;
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}
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/* TODO: MTE check. */
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host_fn(vd, reg_off, info.host);
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}
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} else {
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*(uint32_t *)(vd + H1_4(reg_off)) = 0;
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}
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reg_off += esize;
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} while (reg_off & 63);
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}
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return;
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fault:
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record_fault(env, reg_off, reg_max);
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}
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static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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target_ulong base, uint32_t desc, uintptr_t ra,
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zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
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sve_ld1_nf_fn *nonfault_fn)
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{
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const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
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const int mmu_idx = get_mmuidx(oi);
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const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
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intptr_t reg_off, reg_max = simd_oprsz(desc);
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target_ulong addr;
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/* Skip to the first true predicate. */
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reg_off = find_next_active(vg, 0, reg_max, MO_64);
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if (likely(reg_off < reg_max)) {
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/* Perform one normal read, which will fault or not. */
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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tlb_fn(env, vd, reg_off, addr, ra);
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/* The rest of the reads will be non-faulting. */
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}
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/* After any fault, zero the leading predicated false elements. */
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swap_memzero(vd, reg_off);
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while (likely((reg_off += 8) < reg_max)) {
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uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
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if (likely(pg & 1)) {
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
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record_fault(env, reg_off, reg_max);
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break;
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}
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} else {
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*(uint64_t *)(vd + reg_off) = 0;
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}
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}
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#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
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void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
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void *vm, target_ulong base, uint32_t desc) \
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{ \
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sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
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off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
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}
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#define DO_LDFF1_ZPZ_S(MEM, OFS) \
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void HELPER(sve_ldff##MEM##_##OFS) \
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(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
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off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
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#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
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void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
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void *vm, target_ulong base, uint32_t desc) \
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{ \
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sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
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off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
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}
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#define DO_LDFF1_ZPZ_D(MEM, OFS) \
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void HELPER(sve_ldff##MEM##_##OFS) \
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(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
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off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
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}
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DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
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DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
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DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
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DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
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DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
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DO_LDFF1_ZPZ_S(bsu, zsu)
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DO_LDFF1_ZPZ_S(bsu, zss)
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DO_LDFF1_ZPZ_D(bdu, zsu)
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DO_LDFF1_ZPZ_D(bdu, zss)
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DO_LDFF1_ZPZ_D(bdu, zd)
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DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
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DO_LDFF1_ZPZ_S(bss, zss, MO_8)
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DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
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DO_LDFF1_ZPZ_D(bds, zss, MO_8)
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DO_LDFF1_ZPZ_D(bds, zd, MO_8)
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DO_LDFF1_ZPZ_S(bss, zsu)
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DO_LDFF1_ZPZ_S(bss, zss)
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DO_LDFF1_ZPZ_D(bds, zsu)
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DO_LDFF1_ZPZ_D(bds, zss)
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DO_LDFF1_ZPZ_D(bds, zd)
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DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
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DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
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DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
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DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
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DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
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DO_LDFF1_ZPZ_S(hsu_le, zsu)
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DO_LDFF1_ZPZ_S(hsu_le, zss)
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DO_LDFF1_ZPZ_D(hdu_le, zsu)
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DO_LDFF1_ZPZ_D(hdu_le, zss)
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DO_LDFF1_ZPZ_D(hdu_le, zd)
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DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
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DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
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DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
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DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
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DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
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DO_LDFF1_ZPZ_S(hsu_be, zsu)
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DO_LDFF1_ZPZ_S(hsu_be, zss)
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DO_LDFF1_ZPZ_D(hdu_be, zsu)
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DO_LDFF1_ZPZ_D(hdu_be, zss)
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DO_LDFF1_ZPZ_D(hdu_be, zd)
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DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
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DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
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DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
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DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
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DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
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DO_LDFF1_ZPZ_S(hss_le, zsu)
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DO_LDFF1_ZPZ_S(hss_le, zss)
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DO_LDFF1_ZPZ_D(hds_le, zsu)
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DO_LDFF1_ZPZ_D(hds_le, zss)
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DO_LDFF1_ZPZ_D(hds_le, zd)
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DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
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DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
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DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
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DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
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DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
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DO_LDFF1_ZPZ_S(hss_be, zsu)
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DO_LDFF1_ZPZ_S(hss_be, zss)
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DO_LDFF1_ZPZ_D(hds_be, zsu)
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DO_LDFF1_ZPZ_D(hds_be, zss)
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DO_LDFF1_ZPZ_D(hds_be, zd)
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DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
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DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
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DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
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DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
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DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
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DO_LDFF1_ZPZ_S(ss_le, zsu)
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DO_LDFF1_ZPZ_S(ss_le, zss)
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DO_LDFF1_ZPZ_D(sdu_le, zsu)
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DO_LDFF1_ZPZ_D(sdu_le, zss)
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DO_LDFF1_ZPZ_D(sdu_le, zd)
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DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
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DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
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DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
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DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
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DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
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DO_LDFF1_ZPZ_S(ss_be, zsu)
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DO_LDFF1_ZPZ_S(ss_be, zss)
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DO_LDFF1_ZPZ_D(sdu_be, zsu)
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DO_LDFF1_ZPZ_D(sdu_be, zss)
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DO_LDFF1_ZPZ_D(sdu_be, zd)
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DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
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DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
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DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
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DO_LDFF1_ZPZ_D(sds_le, zsu)
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DO_LDFF1_ZPZ_D(sds_le, zss)
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DO_LDFF1_ZPZ_D(sds_le, zd)
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DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
|
||||
|
||||
DO_LDFF1_ZPZ_D(sds_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zss)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zd)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
|
||||
|
||||
DO_LDFF1_ZPZ_D(dd_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zss)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_D(dd_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zss)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zd)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
|
||||
|
||||
/* Stores with a vector index. */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue