target/mips: Add a comment before each CP0 register section in cpu.h
Add a comment before each CP0 register section in CPUMIPSState definition, thus visually separating these sections. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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Aleksandar Markovic
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a86d421e18
commit
50e7edc5ac
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@ -303,11 +303,17 @@ struct CPUMIPSState {
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* 6 DataLo DataHi KScratch<n>
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* 7 TagLo TagHi KScratch<n>
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*
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*/
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/*
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* CP0 Register 0
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*/
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int32_t CP0_Index;
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/* CP0_MVP* are per MVP registers. */
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int32_t CP0_VPControl;
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#define CP0VPCtl_DIS 0
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/*
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* CP0 Register 1
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*/
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int32_t CP0_Random;
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int32_t CP0_VPEControl;
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#define CP0VPECo_YSI 21
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@ -348,7 +354,13 @@ struct CPUMIPSState {
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#define CP0VPEOpt_DWX2 2
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#define CP0VPEOpt_DWX1 1
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#define CP0VPEOpt_DWX0 0
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/*
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* CP0 Register 2
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*/
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uint64_t CP0_EntryLo0;
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/*
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* CP0 Register 3
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*/
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uint64_t CP0_EntryLo1;
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#if defined(TARGET_MIPS64)
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# define CP0EnLo_RI 63
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@ -359,8 +371,14 @@ struct CPUMIPSState {
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#endif
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int32_t CP0_GlobalNumber;
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#define CP0GN_VPId 0
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/*
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* CP0 Register 4
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*/
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target_ulong CP0_Context;
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target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
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/*
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* CP0 Register 5
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*/
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int32_t CP0_PageMask;
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain;
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@ -398,6 +416,9 @@ struct CPUMIPSState {
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#define CP0SC2_XR 56
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#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
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#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
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/*
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* CP0 Register 6
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*/
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int32_t CP0_Wired;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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@ -428,16 +449,34 @@ struct CPUMIPSState {
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#define CP0SRSC4_SRS15 20
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#define CP0SRSC4_SRS14 10
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#define CP0SRSC4_SRS13 0
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/*
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* CP0 Register 7
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*/
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int32_t CP0_HWREna;
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/*
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* CP0 Register 8
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*/
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target_ulong CP0_BadVAddr;
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uint32_t CP0_BadInstr;
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uint32_t CP0_BadInstrP;
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uint32_t CP0_BadInstrX;
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/*
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* CP0 Register 9
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*/
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int32_t CP0_Count;
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/*
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* CP0 Register 10
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*/
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target_ulong CP0_EntryHi;
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#define CP0EnHi_EHINV 10
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target_ulong CP0_EntryHi_ASID_mask;
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/*
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* CP0 Register 11
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*/
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int32_t CP0_Compare;
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/*
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* CP0 Register 12
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*/
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int32_t CP0_Status;
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#define CP0St_CU3 31
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#define CP0St_CU2 30
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@ -479,6 +518,9 @@ struct CPUMIPSState {
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#define CP0SRSMap_SSV2 8
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#define CP0SRSMap_SSV1 4
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#define CP0SRSMap_SSV0 0
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/*
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* CP0 Register 13
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*/
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int32_t CP0_Cause;
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#define CP0Ca_BD 31
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#define CP0Ca_TI 30
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@ -490,12 +532,21 @@ struct CPUMIPSState {
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#define CP0Ca_IP 8
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#define CP0Ca_IP_mask 0x0000FF00
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#define CP0Ca_EC 2
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/*
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* CP0 Register 14
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*/
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target_ulong CP0_EPC;
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/*
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* CP0 Register 15
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*/
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int32_t CP0_PRid;
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target_ulong CP0_EBase;
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target_ulong CP0_EBaseWG_rw_bitmask;
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#define CP0EBase_WG 11
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target_ulong CP0_CMGCRBase;
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/*
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* CP0 Register 16
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*/
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int32_t CP0_Config0;
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#define CP0C0_M 31
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#define CP0C0_K23 28 /* 30..28 */
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@ -612,6 +663,9 @@ struct CPUMIPSState {
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uint64_t CP0_MAAR[MIPS_MAAR_MAX];
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int32_t CP0_MAARI;
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/* XXX: Maybe make LLAddr per-TC? */
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/*
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* CP0 Register 17
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*/
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uint64_t lladdr;
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target_ulong llval;
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target_ulong llnewval;
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@ -620,11 +674,23 @@ struct CPUMIPSState {
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target_ulong llreg;
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uint64_t CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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/*
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* CP0 Register 18
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*/
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target_ulong CP0_WatchLo[8];
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/*
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* CP0 Register 19
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*/
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int32_t CP0_WatchHi[8];
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#define CP0WH_ASID 16
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/*
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* CP0 Register 20
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*/
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target_ulong CP0_XContext;
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int32_t CP0_Framemask;
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/*
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* CP0 Register 23
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*/
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int32_t CP0_Debug;
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#define CP0DB_DBD 31
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#define CP0DB_DM 30
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@ -644,18 +710,40 @@ struct CPUMIPSState {
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#define CP0DB_DDBL 2
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#define CP0DB_DBp 1
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#define CP0DB_DSS 0
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/*
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* CP0 Register 24
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*/
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target_ulong CP0_DEPC;
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/*
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* CP0 Register 25
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*/
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int32_t CP0_Performance0;
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/*
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* CP0 Register 26
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*/
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int32_t CP0_ErrCtl;
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#define CP0EC_WST 29
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#define CP0EC_SPR 28
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#define CP0EC_ITC 26
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/*
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* CP0 Register 28
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*/
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uint64_t CP0_TagLo;
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int32_t CP0_DataLo;
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/*
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* CP0 Register 29
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*/
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int32_t CP0_TagHi;
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int32_t CP0_DataHi;
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/*
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* CP0 Register 30
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*/
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target_ulong CP0_ErrorEPC;
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/*
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* CP0 Register 31
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*/
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int32_t CP0_DESAVE;
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/* We waste some space so we can handle shadow registers like TCs. */
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TCState tcs[MIPS_SHADOW_SET_MAX];
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CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
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