target/i386: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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ad2ca2e3f7
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5128d58480
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@ -1567,20 +1567,6 @@ illegal:
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return false;
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}
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static void decode_temp_free(X86DecodedOp *op)
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{
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if (op->v_ptr) {
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tcg_temp_free_ptr(op->v_ptr);
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}
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}
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static void decode_temps_free(X86DecodedInsn *decode)
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{
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decode_temp_free(&decode->op[0]);
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decode_temp_free(&decode->op[1]);
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decode_temp_free(&decode->op[2]);
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}
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/*
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* Convert one instruction. s->base.is_jmp is set if the translation must
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* be stopped.
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@ -1835,7 +1821,6 @@ static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
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decode.e.gen(s, env, &decode);
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gen_writeback(s, &decode, 0, s->T0);
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}
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decode_temps_free(&decode);
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return;
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illegal_op:
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gen_illegal_opcode(s);
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@ -629,7 +629,6 @@ static inline void gen_ternary_sse(DisasContext *s, CPUX86State *env, X86Decoded
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/* The format of the fourth input is Lx */
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tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3));
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fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3);
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tcg_temp_free_ptr(ptr3);
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}
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#define TERNARY_SSE(uname, uvname, lname) \
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static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
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@ -1001,7 +1000,6 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX86State *env, X86DecodedIns
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int ymmh_ofs = vector_elem_offset(&decode->op[1], MO_128, 1);
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tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0);
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}
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tcg_temp_free_ptr(index);
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}
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#define VSIB_AVX(uname, lname) \
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static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
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@ -1627,7 +1625,6 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
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tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
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}
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}
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tcg_temp_free(t);
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}
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static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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@ -1762,7 +1759,6 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
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} else {
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gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
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}
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tcg_temp_free_ptr(imm_vec);
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}
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static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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@ -1775,7 +1771,6 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
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} else {
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gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
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}
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tcg_temp_free_ptr(imm_vec);
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}
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static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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@ -2293,7 +2288,6 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
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tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0));
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gen_helper_memset(ptr, ptr, tcg_constant_i32(0),
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tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg)));
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tcg_temp_free_ptr(ptr);
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}
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static void gen_VZEROUPPER(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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@ -899,10 +899,6 @@ static void gen_compute_eflags(DisasContext *s)
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gen_update_cc_op(s);
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gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op);
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set_cc_op(s, CC_OP_EFLAGS);
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if (dead) {
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tcg_temp_free(zero);
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}
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}
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typedef struct CCPrepare {
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@ -1650,7 +1646,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
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} else {
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tcg_gen_mov_tl(cpu_cc_src, shm1);
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}
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tcg_temp_free(z_tl);
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/* Get the two potential CC_OP values into temporaries. */
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tcg_gen_movi_i32(s->tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
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@ -1666,8 +1661,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
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s32 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(s32, count);
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tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
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tcg_temp_free_i32(z32);
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tcg_temp_free_i32(s32);
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/* The CC_OP value is no longer predictable. */
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set_cc_op(s, CC_OP_DYNAMIC);
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@ -1827,8 +1820,6 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
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tcg_gen_movi_i32(s->tmp3_i32, CC_OP_EFLAGS);
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tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0,
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s->tmp2_i32, s->tmp3_i32);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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/* The CC_OP value is no longer predictable. */
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set_cc_op(s, CC_OP_DYNAMIC);
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@ -2049,7 +2040,6 @@ static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,
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gen_op_st_rm_T0_A0(s, ot, op1);
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gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right);
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tcg_temp_free(count);
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}
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static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s)
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@ -2513,13 +2503,6 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
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tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
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s->T0, cpu_regs[reg]);
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gen_op_mov_reg_v(s, ot, reg, s->T0);
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if (cc.mask != -1) {
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tcg_temp_free(cc.reg);
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}
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if (!cc.use_reg2) {
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tcg_temp_free(cc.reg2);
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}
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}
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static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg)
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@ -2748,7 +2731,6 @@ static void gen_set_hflag(DisasContext *s, uint32_t mask)
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_gen_ori_i32(t, t, mask);
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_temp_free_i32(t);
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s->flags |= mask;
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}
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}
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@ -2760,7 +2742,6 @@ static void gen_reset_hflag(DisasContext *s, uint32_t mask)
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_gen_andi_i32(t, t, ~mask);
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_temp_free_i32(t);
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s->flags &= ~mask;
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}
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}
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@ -2772,7 +2753,6 @@ static void gen_set_eflags(DisasContext *s, target_ulong mask)
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tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
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tcg_gen_ori_tl(t, t, mask);
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tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
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tcg_temp_free(t);
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}
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static void gen_reset_eflags(DisasContext *s, target_ulong mask)
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@ -2782,7 +2762,6 @@ static void gen_reset_eflags(DisasContext *s, target_ulong mask)
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tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
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tcg_gen_andi_tl(t, t, ~mask);
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tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
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tcg_temp_free(t);
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}
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/* Clear BND registers during legacy branches. */
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@ -3015,13 +2994,11 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm)
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tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val,
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s->mem_index, MO_TEUQ);
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}
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tcg_temp_free_i64(val);
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/* Set tmp0 to match the required value of Z. */
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tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp);
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Z = tcg_temp_new();
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tcg_gen_trunc_i64_tl(Z, cmp);
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tcg_temp_free_i64(cmp);
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/*
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* Extract the result values for the register pair.
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@ -3042,12 +3019,10 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm)
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero,
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s->T1, cpu_regs[R_EDX]);
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}
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tcg_temp_free_i64(old);
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/* Update Z. */
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gen_compute_eflags(s);
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tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1);
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tcg_temp_free(Z);
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}
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#ifdef TARGET_X86_64
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@ -3072,8 +3047,6 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm)
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}
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tcg_gen_extr_i128_i64(s->T0, s->T1, val);
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tcg_temp_free_i128(cmp);
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tcg_temp_free_i128(val);
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/* Determine success after the fact. */
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t0 = tcg_temp_new_i64();
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@ -3081,13 +3054,11 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm)
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tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]);
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tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]);
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tcg_gen_or_i64(t0, t0, t1);
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tcg_temp_free_i64(t1);
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/* Update Z. */
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gen_compute_eflags(s);
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tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0);
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tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1);
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tcg_temp_free_i64(t0);
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/*
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* Extract the result values for the register pair. We may do this
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@ -3437,10 +3408,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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tcg_gen_neg_tl(t1, t0);
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tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1,
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s->mem_index, ot | MO_LE);
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tcg_temp_free(t1);
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tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1);
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tcg_temp_free(t2);
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tcg_gen_neg_tl(s->T0, t0);
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} else {
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tcg_gen_neg_tl(s->T0, s->T0);
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@ -3927,9 +3896,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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tcg_gen_mov_tl(s->cc_srcT, cmpv);
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tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
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set_cc_op(s, CC_OP_SUBB + ot);
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tcg_temp_free(oldv);
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tcg_temp_free(newv);
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tcg_temp_free(cmpv);
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}
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break;
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case 0x1c7: /* cmpxchg8b */
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@ -4380,7 +4346,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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if (shift) {
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TCGv imm = tcg_const_tl(x86_ldub_code(env, s));
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gen_shiftd_rm_T1(s, ot, opreg, op, imm);
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tcg_temp_free(imm);
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} else {
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gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
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}
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@ -4614,7 +4579,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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tcg_gen_st_tl(last_addr, cpu_env,
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offsetof(CPUX86State, fpdp));
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}
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tcg_temp_free(last_addr);
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} else {
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/* register float ops */
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opreg = rm;
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@ -6279,9 +6243,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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gen_compute_eflags(s);
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tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
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tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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}
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break;
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case 0x102: /* lar */
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@ -6308,7 +6269,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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gen_op_mov_reg_v(s, ot, reg, t0);
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gen_set_label(label1);
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set_cc_op(s, CC_OP_EFLAGS);
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tcg_temp_free(t0);
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}
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break;
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case 0x118:
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@ -6353,7 +6313,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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TCGv_i64 notu = tcg_temp_new_i64();
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tcg_gen_not_i64(notu, cpu_bndu[reg]);
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gen_bndck(env, s, modrm, TCG_COND_GTU, notu);
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tcg_temp_free_i64(notu);
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} else if (prefixes & PREFIX_DATA) {
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/* bndmov -- from reg/mem */
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if (reg >= 4 || s->aflag == MO_16) {
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