OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/riscv: add zicsr/zifencei to isa_string 

Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Hongren (Zenithal) Zheng 2022-05-18 20:46:58 +08:00 committed by Alistair Francis
parent d644e5e44f
commit 5160bacc06
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/riscv/cpu.c
View File

@ -1029,6 +1029,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
* extensions by an underscore.
*/
struct isa_ext_data isa_edata_arr[] = {
ISA_EDATA_ENTRY(zicsr, ext_icsr),
ISA_EDATA_ENTRY(zifencei, ext_ifencei),
ISA_EDATA_ENTRY(zfh, ext_zfh),
ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
ISA_EDATA_ENTRY(zfinx, ext_zfinx),