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target/riscv: Add a riscv_cpu_is_32bit() helper function

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:22:51 -08:00
parent 5b6c291b8d
commit 51ae0cabc6
2 changed files with 11 additions and 0 deletions
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9
target/riscv/cpu.c
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@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
bool riscv_cpu_is_32bit(CPURISCVState *env)
{
if (env->misa & RV64) {
return false;
}
return true;
}
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;

2
target/riscv/cpu.h
View File

@ -384,6 +384,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))