target/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
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@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
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}
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}
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}
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}
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bool riscv_cpu_is_32bit(CPURISCVState *env)
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{
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if (env->misa & RV64) {
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return false;
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}
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return true;
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}
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static void set_misa(CPURISCVState *env, target_ulong misa)
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static void set_misa(CPURISCVState *env, target_ulong misa)
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{
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{
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env->misa_mask = env->misa = misa;
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env->misa_mask = env->misa = misa;
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@ -384,6 +384,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
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/* Is a Hypervisor instruction load/store allowed? */
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/* Is a Hypervisor instruction load/store allowed? */
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FIELD(TB_FLAGS, HLSX, 9, 1)
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FIELD(TB_FLAGS, HLSX, 9, 1)
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bool riscv_cpu_is_32bit(CPURISCVState *env);
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/*
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/*
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* A simplification for VLMAX
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* A simplification for VLMAX
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* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
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* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
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