target/hppa: Convert to TranslatorOps
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Richard Henderson
parent
d01a362528
commit
51b061fbf0
@ -3729,185 +3729,201 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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return gen_illegal(ctx);
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}
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
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CPUState *cs, int max_insns)
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{
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CPUHPPAState *env = cs->env_ptr;
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DisasContext ctx;
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DisasJumpType ret;
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int num_insns, max_insns, i;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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TranslationBlock *tb = ctx->base.tb;
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int i, bound;
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ctx.base.tb = tb;
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ctx.base.singlestep_enabled = cs->singlestep_enabled;
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ctx.cs = cs;
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ctx.iaoq_f = tb->pc;
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ctx.iaoq_b = tb->cs_base;
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ctx->cs = cs;
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ctx->iaoq_f = tb->pc;
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ctx->iaoq_b = tb->cs_base;
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ctx->iaoq_n = -1;
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TCGV_UNUSED(ctx->iaoq_n_var);
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ctx.ntemps = 0;
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for (i = 0; i < ARRAY_SIZE(ctx.temps); ++i) {
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TCGV_UNUSED(ctx.temps[i]);
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ctx->ntemps = 0;
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for (i = 0; i < ARRAY_SIZE(ctx->temps); ++i) {
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TCGV_UNUSED(ctx->temps[i]);
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}
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/* Compute the maximum number of insns to execute, as bounded by
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(1) icount, (2) single-stepping, (3) branch delay slots, or
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(4) the number of insns remaining on the current page. */
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (ctx.base.singlestep_enabled || singlestep) {
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max_insns = 1;
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} else if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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bound = -(tb->pc | TARGET_PAGE_MASK) / 4;
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return MIN(max_insns, bound);
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}
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num_insns = 0;
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gen_tb_start(tb);
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static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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/* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */
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ctx.null_cond = cond_make_f();
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ctx.psw_n_nonzero = false;
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if (tb->flags & 1) {
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ctx.null_cond.c = TCG_COND_ALWAYS;
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ctx.psw_n_nonzero = true;
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ctx->null_cond = cond_make_f();
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ctx->psw_n_nonzero = false;
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if (ctx->base.tb->flags & 1) {
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ctx->null_cond.c = TCG_COND_ALWAYS;
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ctx->psw_n_nonzero = true;
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}
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ctx.null_lab = NULL;
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ctx->null_lab = NULL;
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}
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do {
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tcg_gen_insn_start(ctx.iaoq_f, ctx.iaoq_b);
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num_insns++;
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static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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if (unlikely(cpu_breakpoint_test(cs, ctx.iaoq_f, BP_ANY))) {
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ret = gen_excp(&ctx, EXCP_DEBUG);
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break;
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}
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b);
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}
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if (ctx.iaoq_f < TARGET_PAGE_SIZE) {
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ret = do_page_zero(&ctx);
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assert(ret != DISAS_NEXT);
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static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG);
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ctx->base.pc_next = ctx->iaoq_f + 4;
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return true;
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}
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static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUHPPAState *env = cs->env_ptr;
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DisasJumpType ret;
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int i, n;
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/* Execute one insn. */
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if (ctx->iaoq_f < TARGET_PAGE_SIZE) {
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ret = do_page_zero(ctx);
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assert(ret != DISAS_NEXT);
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} else {
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/* Always fetch the insn, even if nullified, so that we check
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the page permissions for execute. */
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uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f);
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/* Set up the IA queue for the next insn.
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This will be overwritten by a branch. */
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if (ctx->iaoq_b == -1) {
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ctx->iaoq_n = -1;
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ctx->iaoq_n_var = get_temp(ctx);
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tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4);
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} else {
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/* Always fetch the insn, even if nullified, so that we check
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the page permissions for execute. */
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uint32_t insn = cpu_ldl_code(env, ctx.iaoq_f);
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/* Set up the IA queue for the next insn.
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This will be overwritten by a branch. */
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if (ctx.iaoq_b == -1) {
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ctx.iaoq_n = -1;
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ctx.iaoq_n_var = get_temp(&ctx);
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tcg_gen_addi_tl(ctx.iaoq_n_var, cpu_iaoq_b, 4);
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} else {
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ctx.iaoq_n = ctx.iaoq_b + 4;
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TCGV_UNUSED(ctx.iaoq_n_var);
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}
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if (unlikely(ctx.null_cond.c == TCG_COND_ALWAYS)) {
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ctx.null_cond.c = TCG_COND_NEVER;
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ret = DISAS_NEXT;
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} else {
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ret = translate_one(&ctx, insn);
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assert(ctx.null_lab == NULL);
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}
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ctx->iaoq_n = ctx->iaoq_b + 4;
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TCGV_UNUSED(ctx->iaoq_n_var);
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}
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for (i = 0; i < ctx.ntemps; ++i) {
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tcg_temp_free(ctx.temps[i]);
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TCGV_UNUSED(ctx.temps[i]);
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if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) {
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ctx->null_cond.c = TCG_COND_NEVER;
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ret = DISAS_NEXT;
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} else {
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ret = translate_one(ctx, insn);
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assert(ctx->null_lab == NULL);
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}
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ctx.ntemps = 0;
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/* If we see non-linear instructions, exhaust instruction count,
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or run out of buffer space, stop generation. */
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/* ??? The non-linear instruction restriction is purely due to
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the debugging dump. Otherwise we *could* follow unconditional
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branches within the same page. */
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if (ret == DISAS_NEXT
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&& (ctx.iaoq_b != ctx.iaoq_f + 4
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|| num_insns >= max_insns
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|| tcg_op_buf_full())) {
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if (ctx.null_cond.c == TCG_COND_NEVER
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|| ctx.null_cond.c == TCG_COND_ALWAYS) {
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nullify_set(&ctx, ctx.null_cond.c == TCG_COND_ALWAYS);
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gen_goto_tb(&ctx, 0, ctx.iaoq_b, ctx.iaoq_n);
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ret = DISAS_NORETURN;
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} else {
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ret = DISAS_IAQ_N_STALE;
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}
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}
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ctx.iaoq_f = ctx.iaoq_b;
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ctx.iaoq_b = ctx.iaoq_n;
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if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) {
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break;
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}
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if (ctx.iaoq_f == -1) {
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tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b);
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copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_n, ctx.iaoq_n_var);
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nullify_save(&ctx);
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ret = DISAS_IAQ_N_UPDATED;
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break;
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}
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if (ctx.iaoq_b == -1) {
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tcg_gen_mov_tl(cpu_iaoq_b, ctx.iaoq_n_var);
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}
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} while (ret == DISAS_NEXT);
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if (tb->cflags & CF_LAST_IO) {
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gen_io_end();
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}
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switch (ret) {
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/* Free any temporaries allocated. */
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for (i = 0, n = ctx->ntemps; i < n; ++i) {
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tcg_temp_free(ctx->temps[i]);
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TCGV_UNUSED(ctx->temps[i]);
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}
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ctx->ntemps = 0;
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/* Advance the insn queue. */
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/* ??? The non-linear instruction restriction is purely due to
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the debugging dump. Otherwise we *could* follow unconditional
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branches within the same page. */
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if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) {
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if (ctx->null_cond.c == TCG_COND_NEVER
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|| ctx->null_cond.c == TCG_COND_ALWAYS) {
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nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS);
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gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n);
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ret = DISAS_NORETURN;
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} else {
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ret = DISAS_IAQ_N_STALE;
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}
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}
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ctx->iaoq_f = ctx->iaoq_b;
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ctx->iaoq_b = ctx->iaoq_n;
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ctx->base.is_jmp = ret;
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if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) {
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return;
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}
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if (ctx->iaoq_f == -1) {
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tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b);
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copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
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nullify_save(ctx);
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ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
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} else if (ctx->iaoq_b == -1) {
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tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var);
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}
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}
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static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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switch (ctx->base.is_jmp) {
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case DISAS_NORETURN:
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break;
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case DISAS_TOO_MANY:
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case DISAS_IAQ_N_STALE:
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copy_iaoq_entry(cpu_iaoq_f, ctx.iaoq_f, cpu_iaoq_f);
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copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_b, cpu_iaoq_b);
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nullify_save(&ctx);
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copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
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copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
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nullify_save(ctx);
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/* FALLTHRU */
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case DISAS_IAQ_N_UPDATED:
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if (ctx.base.singlestep_enabled) {
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if (ctx->base.singlestep_enabled) {
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gen_excp_1(EXCP_DEBUG);
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} else {
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tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f);
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}
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break;
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default:
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abort();
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g_assert_not_reached();
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}
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gen_tb_end(tb, num_insns);
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/* We don't actually use this during normal translation,
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but we should interact with the generic main loop. */
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ctx->base.pc_next = ctx->base.tb->pc + 4 * ctx->base.num_insns;
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}
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tb->size = num_insns * 4;
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tb->icount = num_insns;
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static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
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{
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TranslationBlock *tb = dcbase->tb;
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(tb->pc)) {
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qemu_log_lock();
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switch (tb->pc) {
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case 0x00:
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qemu_log("IN:\n0x00000000: (null)\n\n");
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break;
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case 0xb0:
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qemu_log("IN:\n0x000000b0: light-weight-syscall\n\n");
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break;
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case 0xe0:
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qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n\n");
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break;
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case 0x100:
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qemu_log("IN:\n0x00000100: syscall\n\n");
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break;
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default:
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qemu_log("IN: %s\n", lookup_symbol(tb->pc));
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log_target_disas(cs, tb->pc, tb->size, 1);
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qemu_log("\n");
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break;
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}
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qemu_log_unlock();
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switch (tb->pc) {
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case 0x00:
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qemu_log("IN:\n0x00000000: (null)\n");
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break;
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case 0xb0:
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qemu_log("IN:\n0x000000b0: light-weight-syscall\n");
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break;
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case 0xe0:
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qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n");
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break;
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case 0x100:
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qemu_log("IN:\n0x00000100: syscall\n");
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break;
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default:
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qemu_log("IN: %s\n", lookup_symbol(tb->pc));
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log_target_disas(cs, tb->pc, tb->size, 1);
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break;
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}
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#endif
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}
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static const TranslatorOps hppa_tr_ops = {
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.init_disas_context = hppa_tr_init_disas_context,
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.tb_start = hppa_tr_tb_start,
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.insn_start = hppa_tr_insn_start,
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.breakpoint_check = hppa_tr_breakpoint_check,
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.translate_insn = hppa_tr_translate_insn,
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.tb_stop = hppa_tr_tb_stop,
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.disas_log = hppa_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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DisasContext ctx;
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translator_loop(&hppa_tr_ops, &ctx.base, cs, tb);
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}
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void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
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