hw/block/nvme: factor out cmb setup
Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Message-Id: <20200609190333.59390-17-its@irrelevant.dk> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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@ -56,6 +56,7 @@
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#define NVME_REG_SIZE 0x1000
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#define NVME_REG_SIZE 0x1000
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#define NVME_DB_SIZE 4
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#define NVME_DB_SIZE 4
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#define NVME_CMB_BIR 2
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#define NVME_GUEST_ERR(trace, fmt, ...) \
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#define NVME_GUEST_ERR(trace, fmt, ...) \
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do { \
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do { \
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@ -1438,6 +1439,28 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
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id_ns->nuse = id_ns->ncap;
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id_ns->nuse = id_ns->ncap;
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}
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}
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static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
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{
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NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR);
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NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
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NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
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NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
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NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
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NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
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n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
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memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
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"nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
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pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
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}
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static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
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static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
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{
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{
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uint8_t *pci_conf = pci_dev->config;
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uint8_t *pci_conf = pci_dev->config;
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@ -1514,25 +1537,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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n->bar.intmc = n->bar.intms = 0;
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n->bar.intmc = n->bar.intms = 0;
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if (n->params.cmb_size_mb) {
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if (n->params.cmb_size_mb) {
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nvme_init_cmb(n, pci_dev);
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NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2);
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NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
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NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
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NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
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NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
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NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
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NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
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n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
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memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
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"nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
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pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
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PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
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} else if (n->pmrdev) {
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} else if (n->pmrdev) {
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/* Controller Capabilities register */
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/* Controller Capabilities register */
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NVME_CAP_SET_PMRS(n->bar.cap, 1);
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NVME_CAP_SET_PMRS(n->bar.cap, 1);
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