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target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro

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Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240129164514.73104-29-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2024-01-29 17:45:10 +01:00 committed by Thomas Huth
parent 39ac0bac99
commit 52049266e5
6 changed files with 10 additions and 20 deletions
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3
target/xtensa/cpu.c
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@ -96,9 +96,8 @@ bool xtensa_abi_call0(void)
static void xtensa_cpu_reset_hold(Object *obj) static void xtensa_cpu_reset_hold(Object *obj)
{ {
CPUState *cs = CPU(obj); CPUState *cs = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(cs);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
CPUXtensaState *env = &cpu->env; CPUXtensaState *env = cpu_env(cs);
bool dfpu = xtensa_option_enabled(env->config, bool dfpu = xtensa_option_enabled(env->config,
XTENSA_OPTION_DFP_COPROCESSOR); XTENSA_OPTION_DFP_COPROCESSOR);

3
target/xtensa/dbg_helper.c
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@ -66,8 +66,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
bool xtensa_debug_check_breakpoint(CPUState *cs) bool xtensa_debug_check_breakpoint(CPUState *cs)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
unsigned int i; unsigned int i;
if (xtensa_get_cintlevel(env) >= env->config->debug_level) { if (xtensa_get_cintlevel(env) >= env->config->debug_level) {

3
target/xtensa/exc_helper.c
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@ -205,8 +205,7 @@ static void handle_interrupt(CPUXtensaState *env)
/* Called from cpu_handle_interrupt with BQL held */ /* Called from cpu_handle_interrupt with BQL held */
void xtensa_cpu_do_interrupt(CPUState *cs) void xtensa_cpu_do_interrupt(CPUState *cs)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
if (cs->exception_index == EXC_IRQ) { if (cs->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT, qemu_log_mask(CPU_LOG_INT,

6
target/xtensa/gdbstub.c
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@ -65,8 +65,7 @@ void xtensa_count_regs(const XtensaConfig *config,
int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
int num_regs = env->config->gdb_regmap.num_core_regs; int num_regs = env->config->gdb_regmap.num_core_regs;
@ -120,8 +119,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
uint32_t tmp; uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY

9
target/xtensa/helper.c
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@ -217,8 +217,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env)
void xtensa_breakpoint_handler(CPUState *cs) void xtensa_breakpoint_handler(CPUState *cs)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
if (cs->watchpoint_hit) { if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) { if (cs->watchpoint_hit->flags & BP_CPU) {
@ -266,8 +265,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx, MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr) bool probe, uintptr_t retaddr)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
uint32_t paddr; uint32_t paddr;
uint32_t page_size; uint32_t page_size;
unsigned access; unsigned access;
@ -297,8 +295,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs, int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr) MemTxResult response, uintptr_t retaddr)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
cpu_restore_state(cs, retaddr); cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, HELPER(exception_cause_vaddr)(env, env->pc,

6
target/xtensa/translate.c
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@ -1127,10 +1127,9 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu) CPUState *cpu)
{ {
DisasContext *dc = container_of(dcbase, DisasContext, base); DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags; uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config; dc->config = cpu_env(cpu)->config;
dc->pc = dc->base.pc_first; dc->pc = dc->base.pc_first;
dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
@ -1248,8 +1247,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = cpu_env(cs);
CPUXtensaState *env = &cpu->env;
xtensa_isa isa = env->config->isa; xtensa_isa isa = env->config->isa;
int i, j; int i, j;