Make detection of unsupported hosts easier, inspired by a patch from
Stefan Weil. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2791 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -89,21 +89,19 @@ extern int printf(const char *, ...);
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#undef NULL
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#define NULL 0
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#ifdef __i386__
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#if defined(__i386__)
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#define AREG0 "ebp"
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#define AREG1 "ebx"
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#define AREG2 "esi"
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#define AREG3 "edi"
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#endif
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#ifdef __x86_64__
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#elif defined(__x86_64__)
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#define AREG0 "r14"
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#define AREG1 "r15"
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#define AREG2 "r12"
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#define AREG3 "r13"
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//#define AREG4 "rbp"
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//#define AREG5 "rbx"
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#endif
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#ifdef __powerpc__
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#elif defined(__powerpc__)
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#define AREG0 "r27"
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#define AREG1 "r24"
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#define AREG2 "r25"
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@ -121,14 +119,12 @@ extern int printf(const char *, ...);
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#endif
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#define USE_INT_TO_FLOAT_HELPERS
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#define BUGGY_GCC_DIV64
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#endif
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#ifdef __arm__
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#elif defined(__arm__)
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#define AREG0 "r7"
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#define AREG1 "r4"
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#define AREG2 "r5"
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#define AREG3 "r6"
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#endif
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#ifdef __mips__
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#elif defined(__mips__)
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#define AREG0 "fp"
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#define AREG1 "s0"
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#define AREG2 "s1"
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@ -138,8 +134,7 @@ extern int printf(const char *, ...);
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#define AREG6 "s5"
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#define AREG7 "s6"
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#define AREG8 "s7"
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#endif
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#ifdef __sparc__
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#elif defined(__sparc__)
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#ifdef HOST_SOLARIS
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#define AREG0 "g2"
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#define AREG1 "g3"
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@ -168,14 +163,12 @@ extern int printf(const char *, ...);
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#endif
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#endif
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#define USE_FP_CONVERT
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#endif
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#ifdef __s390__
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#elif defined(__s390__)
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#define AREG0 "r10"
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#define AREG1 "r7"
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#define AREG2 "r8"
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#define AREG3 "r9"
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#endif
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#ifdef __alpha__
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#elif defined(__alpha__)
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/* Note $15 is the frame pointer, so anything in op-i386.c that would
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require a frame pointer, like alloca, would probably loose. */
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#define AREG0 "$15"
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@ -185,19 +178,19 @@ extern int printf(const char *, ...);
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#define AREG4 "$12"
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#define AREG5 "$13"
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#define AREG6 "$14"
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#endif
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#ifdef __mc68000
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#elif defined(__mc68000)
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#define AREG0 "%a5"
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#define AREG1 "%a4"
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#define AREG2 "%d7"
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#define AREG3 "%d6"
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#define AREG4 "%d5"
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#endif
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#ifdef __ia64__
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#elif defined(__ia64__)
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#define AREG0 "r7"
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#define AREG1 "r4"
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#define AREG2 "r5"
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#define AREG3 "r6"
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#else
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#error unsupported CPU
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#endif
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/* force GCC to generate only one epilog at the end of the function */
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@ -250,44 +243,37 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#define ASM_NAME(x) #x
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#endif
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#ifdef __i386__
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#if defined(__i386__)
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#define EXIT_TB() asm volatile ("ret")
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#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __x86_64__
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#elif defined(__x86_64__)
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#define EXIT_TB() asm volatile ("ret")
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#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __powerpc__
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#elif defined(__powerpc__)
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#define EXIT_TB() asm volatile ("blr")
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#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __s390__
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#elif defined(__s390__)
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#define EXIT_TB() asm volatile ("br %r14")
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#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __alpha__
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#elif defined(__alpha__)
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#define EXIT_TB() asm volatile ("ret")
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#endif
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#ifdef __ia64__
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#elif defined(__ia64__)
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#define EXIT_TB() asm volatile ("br.ret.sptk.many b0;;")
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#define GOTO_LABEL_PARAM(n) asm volatile ("br.sptk.many " \
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ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __sparc__
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#elif defined(__sparc__)
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#define EXIT_TB() asm volatile ("jmpl %i0 + 8, %g0; nop")
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#define GOTO_LABEL_PARAM(n) asm volatile ("ba " ASM_NAME(__op_gen_label) #n ";nop")
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#endif
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#ifdef __arm__
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#elif defined(__arm__)
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#define EXIT_TB() asm volatile ("b exec_loop")
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#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n)
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#endif
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#ifdef __mc68000
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#elif defined(__mc68000)
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#define EXIT_TB() asm volatile ("rts")
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#endif
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#ifdef __mips__
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#elif defined(__mips__)
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#define EXIT_TB() asm volatile ("jr $ra")
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#define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at")
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#else
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#error unsupported CPU
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#endif
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#endif /* !defined(__DYNGEN_EXEC_H__) */
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59
dyngen.h
59
dyngen.h
@ -28,25 +28,11 @@ int __op_param1, __op_param2, __op_param3;
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#endif
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int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#ifdef __i386__
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __x86_64__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __s390__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __ia64__
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#elif defined(__ia64__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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while (start < stop) {
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@ -55,9 +41,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop)
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}
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asm volatile (";;sync.i;;srlz.i;;");
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}
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#endif
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#ifdef __powerpc__
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#elif defined(__powerpc__)
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
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@ -78,17 +62,12 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop)
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#endif
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#ifdef __alpha__
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#elif defined(__alpha__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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asm ("imb");
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}
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#endif
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#ifdef __sparc__
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#elif defined(__sparc__)
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long p;
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@ -99,10 +78,7 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop)
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for (; p < stop; p += 8)
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__asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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#endif
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#ifdef __arm__
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#elif defined(__arm__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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register unsigned long _beg __asm ("a1") = start;
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@ -110,14 +86,22 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop)
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register unsigned long _flg __asm ("a3") = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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}
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#endif
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#elif defined(__mc68000)
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#ifdef __mc68000
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#include <asm/cachectl.h>
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# include <asm/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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}
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#elif defined(__mips__)
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#include <sys/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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_flush_cache ((void *)start, stop - start, BCACHE);
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}
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#else
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#error unsupported CPU
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#endif
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#ifdef __alpha__
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@ -248,7 +232,6 @@ static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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#ifdef __ia64
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/* Patch instruction with "val" where "mask" has 1 bits. */
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static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
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{
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@ -463,11 +446,3 @@ static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
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}
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#endif
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#ifdef __mips__
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#include <sys/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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_flush_cache ((void *)start, stop - start, BCACHE);
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}
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#endif
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